Patents by Inventor Yoko Chiba
Yoko Chiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240121589Abstract: A unit is provided through an application of a disaster condition to a PLMN in 5GS, the unit being for transmitting and/or receiving a notification in a case that a communication service cannot be provided to a UE and for selecting a roaming destination PLMN by the UE. Provided are a procedure to allow the UE to recognize a state of a certain PLMN and transmit and/or receive information for appropriately selecting a PLMN as a moving destination in a case that a disaster condition applies or no longer applies to the certain PLMN, a method of selecting a PLMN based on information received and stored by the UE through a notification from the PLMN or the like, and a communication unit.Type: ApplicationFiled: January 14, 2022Publication date: April 11, 2024Inventors: SHUICHIRO CHIBA, YASUO SUGAWARA, YUDAI KAWASAKI, YOKO KUGE
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Publication number: 20240114587Abstract: A User Equipment (UE) includes transmission and reception circuitry, and a controller, wherein while one or more Tsor-cm timers are running, and upon receiving a new Steering of roaming connected mode control information (SOR-CMCI), the controller sets a Tsor-cm timer value for an associated PDU session or service to a timer value in the new SOR-CMCI.Type: ApplicationFiled: December 22, 2021Publication date: April 4, 2024Inventors: YOKO KUGE, YASUO SUGAWARA, YUDAI KAWASAKI, SHUICHIRO CHIBA, Masaki IZUMI, MASAFUMI ARAMOTO
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Publication number: 20240098841Abstract: In a case that user equipment (UE) that has established a communication path for direct C2 communication receives, from a network, a PDU session release command message for revoking authentication and/or authorization of the communication path for the direct C2 communication or a PDU session modification command message, the UE can indicate an appropriate cause value in the procedure of releasing the communication path for the direct C2 communication.Type: ApplicationFiled: February 9, 2023Publication date: March 21, 2024Inventors: SHUICHIRO CHIBA, YASUO SUGAWARA, YOKO KUGE, Masaki IZUMI
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Publication number: 20240073803Abstract: A unit is provided through an application of a disaster condition to a PLMN in 5GS, the unit being for transmitting and/or receiving a notification in a case that a communication service cannot be provided to a UE and for selecting a roaming destination PLMN by the UE. Provided are a procedure to allow the UE to recognize a state of a certain PLMN and transmit and/or receive information for appropriately selecting a PLMN as a moving destination in a case that a disaster condition applies or no longer applies to the certain PLMN, a method of selecting a PLMN based on information received and stored by the UE through a notification from the PLMN or the like, and a communication unit.Type: ApplicationFiled: January 14, 2022Publication date: February 29, 2024Inventors: SHUICHIRO CHIBA, YASUO SUGAWARA, YUDAI KAWASAKI, YOKO KUGE
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Publication number: 20230187453Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
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Patent number: 11610918Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: GrantFiled: December 5, 2019Date of Patent: March 21, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Publication number: 20220020841Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
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Patent number: 11139359Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.Type: GrantFiled: October 18, 2016Date of Patent: October 5, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Publication number: 20200111816Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
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Patent number: 10559599Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: GrantFiled: June 21, 2018Date of Patent: February 11, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Publication number: 20180315779Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: ApplicationFiled: June 21, 2018Publication date: November 1, 2018Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
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Patent number: 10032796Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: GrantFiled: March 8, 2016Date of Patent: July 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Publication number: 20170040409Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
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Patent number: 9564517Abstract: To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, a step of lifting off using a halftone mask or a gray-tone mask and a step of reflowing a photoresist are used.Type: GrantFiled: May 20, 2014Date of Patent: February 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kunio Hosoya, Saishi Fujikawa, Yoko Chiba
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Patent number: 9478597Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.Type: GrantFiled: September 10, 2009Date of Patent: October 25, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Publication number: 20160190177Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Rihito WADA, Yoko CHIBA
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Patent number: 9343517Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.Type: GrantFiled: February 3, 2011Date of Patent: May 17, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Patent number: 8895333Abstract: The number of photomasks is reduced in a method for manufacturing a liquid crystal display device which operates in a fringe field switching mode, whereby a manufacturing process is simplified and manufacturing cost is reduced. A first transparent conductive film and a first metal film are sequentially stacked over a light-transmitting insulating substrate; the first transparent conductive film and the first metal film are shaped using a multi-tone mask which is a first photomask; an insulating film, a first semiconductor film, a second semiconductor film, and a second metal film are sequentially stacked; the second metal film and the second semiconductor film are shaped using a multi-tone mask which is a second photomask; a protective film is formed; the protective film is shaped using a third photomask; a second transparent conductive film is formed; and the second transparent conductive film is shaped using a fourth photomask.Type: GrantFiled: September 5, 2012Date of Patent: November 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Saishi Fujikawa, Yoko Chiba
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Publication number: 20140256095Abstract: To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, a step of lifting off using a halftone mask or a gray-tone mask and a step of reflowing a photoresist are used.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kunio Hosoya, Saishi Fujikawa, Yoko Chiba
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Patent number: 8427595Abstract: To provide a structure suitable for a common connection portion provided in a display panel. A common connection portion provided in an outer region of a pixel portion has a stacked structure of an insulating layer formed using the same layer as a gate insulating layer, an oxide semiconductor layer formed using the same layer as a second oxide semiconductor layer, and a conductive layer (also referred to as a common potential line) formed using the same layer as the conductive layer, in which the conductive layer (also referred to as the common potential line) is connected to a common electrode through an opening in an interlayer insulating layer provided over the first oxide semiconductor layer and an electrode opposite to a pixel electrode is electrically connected to the common electrode through conductive particles.Type: GrantFiled: September 10, 2009Date of Patent: April 23, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba