Patents by Inventor Yoko DEGUCHI
Yoko DEGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11114166Abstract: According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.Type: GrantFiled: September 5, 2019Date of Patent: September 7, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Okuyama, Yoshihiko Kamata, Hiromitsu Komai, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Hiroyuki Kaga
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Patent number: 10957403Abstract: A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.Type: GrantFiled: August 23, 2019Date of Patent: March 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoko Deguchi, Masahiro Yoshihara, Yoshihiko Kamata, Takuyo Kodama
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Patent number: 10861536Abstract: A semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage, higher than the first voltage, to the bit line, and also apply a third voltage, lower than the first voltage, to the source line in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.Type: GrantFiled: September 4, 2019Date of Patent: December 8, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
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Patent number: 10755791Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.Type: GrantFiled: March 4, 2019Date of Patent: August 25, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
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Patent number: 10720220Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense amplifier connected to the memory cell through the bit line, and a control circuit. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node and a sense transistor having a gate connected to the sense node. The control circuit is configured to adjust a voltage applied to a back gate of the sense transistor or a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor.Type: GrantFiled: April 17, 2019Date of Patent: July 21, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Yoko Deguchi, Takuyo Kodama, Tsukasa Kobayashi, Mario Sako, Kosuke Yanagidaira
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Publication number: 20200202948Abstract: According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.Type: ApplicationFiled: September 5, 2019Publication date: June 25, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Atsushi OKUYAMA, Yoshihiko KAMATA, Hiromitsu KOMAI, Takuyo KODAMA, Yuki ISHIZAKI, Yoko DEGUCHI, Hiroyuki KAGA
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Publication number: 20200202956Abstract: A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.Type: ApplicationFiled: August 23, 2019Publication date: June 25, 2020Inventors: Yoko DEGUCHI, Masahiro YOSHIHARA, Yoshihiko KAMATA, Takuyo KODAMA
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Publication number: 20200135271Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation being read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage higher than the first voltage to the bit line and also apply a third voltage lower than the first voltage to the source line, in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.Type: ApplicationFiled: September 4, 2019Publication date: April 30, 2020Applicant: Toshiba Memory CorporationInventors: Yoshihiko KAMATA, Takuyo KODAMA, Yuki ISHIZAKI, Yoko DEGUCHI
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Publication number: 20200098435Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.Type: ApplicationFiled: March 4, 2019Publication date: March 26, 2020Applicant: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
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Patent number: 10553283Abstract: According to one embodiment, a semiconductor storage device includes a first plane having a first plurality of memory cells, a second plane having a second plurality of memory cells, first bit lines which are connected to the first plane, second bit lines which are connected to the second plane, a plurality of first sense amplifiers which charge the plurality of first bit lines, and a plurality of second sense amplifiers which charge the plurality of second bit lines. When the first and second planes operate in parallel, a total sum of currents supplied to the plurality of first bit lines from the plurality of first sense amplifiers and currents supplied to the plurality of second bit lines from the plurality of second sense amplifiers reaches a first current value, then decreases to a second current value, and then increases to a third current value.Type: GrantFiled: August 29, 2018Date of Patent: February 4, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoko Deguchi, Kosuke Yanagidaira, Tadashi Yasufuku, Takuyo Kodama
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Publication number: 20190355421Abstract: According to one embodiment, a semiconductor storage device includes a first plane having a first plurality of memory cells, a second plane having a second plurality of memory cells, first bit lines which are connected to the first plane, second bit lines which are connected to the second plane, a plurality of first sense amplifiers which charge the plurality of first bit lines, and a plurality of second sense amplifiers which charge the plurality of second bit lines. When the first and second planes operate in parallel, a total sum of currents supplied to the plurality of first bit lines from the plurality of first sense amplifiers and currents supplied to the plurality of second bit lines from the plurality of second sense amplifiers reaches a first current value, then decreases to a second current value, and then increases to a third current value.Type: ApplicationFiled: August 29, 2018Publication date: November 21, 2019Inventors: Yoko DEGUCHI, Kosuke YANAGIDAIRA, Tadashi YASUFUKU, Takuyo KODAMA
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Publication number: 20190244671Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense amplifier connected to the memory cell through the bit line, and a control circuit. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node and a sense transistor having a gate connected to the sense node. The control circuit is configured to adjust a voltage applied to a back gate of the sense transistor or a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: Yoshihiko KAMATA, Yoko DEGUCHI, Takuyo KODAMA, Tsukasa KOBAYASHI, Mario SAKO, Kosuke YANAGIDAIRA
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Patent number: 10297326Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node, and a static latch circuit connected to the sense node and retains data of the sense node.Type: GrantFiled: January 20, 2017Date of Patent: May 21, 2019Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Yoko Deguchi, Takuyo Kodama, Tsukasa Kobayashi, Mario Sako, Kosuke Yanagidaira
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Publication number: 20170365348Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node, and a static latch circuit connected to the sense node and retains data of the sense node.Type: ApplicationFiled: January 20, 2017Publication date: December 21, 2017Inventors: Yoshihiko KAMATA, Yoko DEGUCHI, Takuyo KODAMA, Tsukasa KOBAYASHI, Mario SAKO, Kosuke YANAGIDAIRA