Patents by Inventor Yoko Sakiyama

Yoko Sakiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210095386
    Abstract: The purpose of the present invention is to provide a composite electrolyte membrane which has excellent chemical resistance and can maintain sufficient mechanical strength even under conditions of high humidity and high pressure, which are the operating conditions for electrochemical hydrogen pumps and water electrolyzers. This composite electrolyte membrane, which is for achieving said purpose, has a composite layer obtained by combining a polyelectrolyte with a mesh woven material that satisfies (1) and (2) and comprises liquid crystal polyester fibers or polyphenylene sulfide fibers. (1): Mesh thickness (?m)/fiber diameter (?m)<2.0. (2): Opening (?m)/fiber diameter (?m)>1.0.
    Type: Application
    Filed: March 25, 2019
    Publication date: April 1, 2021
    Applicant: Toray Industries, Inc.
    Inventors: Kenta Minamibayashi, Yoshitsugu Funatsu, Yoko Sakiyama, Daisuke Ogata, Daisuke Izuhara
  • Patent number: 9190368
    Abstract: According to embodiments, a semiconductor device includes an insulating substrate, a first electrode plate disposed on the insulating substrate, a second electrode plate disposed on the insulating substrate, a third electrode plate disposed on the insulating substrate, a first semiconductor element disposed on the first electrode plate, a first electrode of the first semiconductor element being electrically connected to the first electrode plate, a second semiconductor element disposed on the second electrode plate, a first electrode of the second semiconductor element being electrically connected to the second electrode plate, a first bonding wire electrically connecting a second electrode of the first semiconductor element to the third electrode plate, and a second bonding wire electrically connecting a second electrode of the second semiconductor element to the third electrode plate.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: November 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoko Sakiyama
  • Publication number: 20140284617
    Abstract: According to embodiments, a semiconductor device includes an insulating substrate, a first electrode plate disposed on the insulating substrate, a second electrode plate disposed on the insulating substrate, a third electrode plate disposed on the insulating substrate, a first semiconductor element disposed on the first electrode plate, a first electrode of the first semiconductor element being electrically connected to the first electrode plate, a second semiconductor element disposed on the second electrode plate, a first electrode of the second semiconductor element being electrically connected to the second electrode plate, a first bonding wire electrically connecting a second electrode of the first semiconductor element to the third electrode plate, and a second bonding wire electrically connecting a second electrode of the second semiconductor element to the third electrode plate.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoko SAKIYAMA
  • Patent number: 8823053
    Abstract: The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Sakiyama, Kohei Morizuka
  • Publication number: 20140077260
    Abstract: The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.
    Type: Application
    Filed: February 28, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoko SAKIYAMA, Kohei MORIZUKA
  • Patent number: 7772641
    Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
  • Publication number: 20070210350
    Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 13, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
  • Patent number: D503149
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: March 22, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Teramae, Yoko Sakiyama