Patents by Inventor Yonatan Tzafrir
Yonatan Tzafrir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11387831Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.Type: GrantFiled: January 19, 2021Date of Patent: July 12, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yonatan Tzafrir, Mordekhay Zehavi, Eyal Widder
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Publication number: 20210143821Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.Type: ApplicationFiled: January 19, 2021Publication date: May 13, 2021Inventors: Yonatan TZAFRIR, Mordekhay ZEHAVI, Eyal WIDDER
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Patent number: 10924113Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.Type: GrantFiled: April 26, 2018Date of Patent: February 16, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yonatan Tzafrir, Mordekhay Zehavi, Eyal Widder
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Patent number: 10635131Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.Type: GrantFiled: October 15, 2018Date of Patent: April 28, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Yonatan Tzafrir
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Publication number: 20190341120Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.Type: ApplicationFiled: May 3, 2018Publication date: November 7, 2019Inventors: Mordekhay ZEHAVI, Mahmud ASFUR, Yonatan TZAFRIR
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Patent number: 10466920Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.Type: GrantFiled: August 17, 2017Date of Patent: November 5, 2019Assignee: Western Digital Technologies, Inc.Inventors: Yonatan Tzafrir, Mordekhay Zehavi, Mahmud Asfur
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Patent number: 10446254Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.Type: GrantFiled: May 3, 2018Date of Patent: October 15, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.Inventors: Mordekhay Zehavi, Mahmud Asfur, Yonatan Tzafrir
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Publication number: 20190058474Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.Type: ApplicationFiled: April 26, 2018Publication date: February 21, 2019Inventors: Yonatan TZAFRIR, Mordekhay ZEHAVI, Eyal WIDDER
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Publication number: 20190056880Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Inventors: Yonatan TZAFRIR, Mordekhay ZEHAVI, Mahmud ASFUR
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Publication number: 20190050022Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.Type: ApplicationFiled: October 15, 2018Publication date: February 14, 2019Inventor: Yonatan TZAFRIR
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Patent number: 10198383Abstract: A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.Type: GrantFiled: December 31, 2016Date of Patent: February 5, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Mordekhay Zehavi, Yonatan Tzafrir, Mahmud Asfur
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Patent number: 10101763Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.Type: GrantFiled: July 29, 2015Date of Patent: October 16, 2018Assignee: SANDISK TECHNOLOGIES INC.Inventor: Yonatan Tzafrir
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Patent number: 10042416Abstract: A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are disclosed.Type: GrantFiled: July 20, 2015Date of Patent: August 7, 2018Assignee: SanDisk Technologies LLCInventors: Yonatan Tzafrir, Hannon Aharon Borukhov
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Publication number: 20180189211Abstract: A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.Type: ApplicationFiled: December 31, 2016Publication date: July 5, 2018Inventors: MORDEKHAY ZEHAVI, YONATAN TZAFRIR, MAHMUD ASFUR
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Publication number: 20170031845Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.Type: ApplicationFiled: July 29, 2015Publication date: February 2, 2017Inventor: YONATAN TZAFRIR
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Publication number: 20170024002Abstract: A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are disclosed.Type: ApplicationFiled: July 20, 2015Publication date: January 26, 2017Applicant: SanDisk Technologies Inc.Inventors: Yonatan Tzafrir, Hannon Aharon Borukhov
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Patent number: 9355929Abstract: A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to or exceeds a temperature threshold. A metablock is defined to include a first plurality of storage blocks that includes a first storage block of the first die. Each storage block of the metablock resides in a distinct die of the plurality of dies. The method also includes, in response to detecting that the first temperature is equal to or exceeds the temperature threshold, redefining the metablock to exclude from the redefined metablock any storage block associated with the first die.Type: GrantFiled: April 25, 2012Date of Patent: May 31, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventor: Yonatan Tzafrir
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Patent number: 9336130Abstract: Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.Type: GrantFiled: November 30, 2011Date of Patent: May 10, 2016Assignee: SanDisk Technologies Inc.Inventors: Mahmud Asfur, Yonatan Tzafrir
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Publication number: 20130290600Abstract: A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to or exceeds a temperature threshold. A metablock is defined to include a first plurality of storage blocks that includes a first storage block of the first die. Each storage block of the metablock resides in a distinct die of the plurality of dies. The method also includes, in response to detecting that the first temperature is equal to or exceeds the temperature threshold, redefining the metablock to exclude from the redefined metablock any storage block associated with the first die.Type: ApplicationFiled: April 25, 2012Publication date: October 31, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventor: YONATAN TZAFRIR
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Patent number: 8536471Abstract: A pressure sensitive stylus, comprises a movable tip that recedes within a housing of the stylus in response to user applied contact pressure, wherein a displacement of the tip along an axis on which it recedes is a function of the applied contact pressure, and an optical sensor enclosed within the housing for optically sensing the displacement of the tip and for providing output in response to the sensing.Type: GrantFiled: August 25, 2009Date of Patent: September 17, 2013Assignee: N-trig Ltd.Inventors: Yuval Stern, Rafi Zachut, Yonatan Tzafrir, Eytan Mann, Oran Tamir, Alex Kalmanovich