Patents by Inventor Yonetaro Totsuka
Yonetaro Totsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7475261Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: February 2, 2004Date of Patent: January 6, 2009Assignee: Renesas Technology Corp.Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
-
Publication number: 20080259199Abstract: Disclosed herein is an image display system including a display apparatus, an imaging apparatus placed on a movable body; and a server apparatus. The display apparatus and the imaging apparatus are capable of communicating with the server apparatus. The imaging apparatus includes: an imaging section; a speed detection section; and a control section that controls transmission of image data and speed information to the server apparatus. The server apparatus includes: a movable body speed management section that manages the moving speed of the movable body using the speed information; and a control section that identifies an imaging apparatus that matches speed specification information, and causes image data to be transferred from the identified imaging apparatus to the display apparatus. The display apparatus includes: a display section; and a control section that performs a speed specification process, an image request transmission process, and a display process.Type: ApplicationFiled: October 29, 2007Publication date: October 23, 2008Applicant: Sony CorporationInventors: Yoichiro Sako, Keiji Kimura, Masaaki Tsuruta, Masamichi Asukai, Taiji Ito, Nozomu Ozaki, Akinobu Sugino, Hidehiko Sekizawa, Yonetaro Totsuka
-
Patent number: 7421190Abstract: The present invention is particularly applied to a video tape recorder for recording a video signal of an HDTV (high-definition television) on a magnetic tape. In the video tape recorder, the recording position of the head of each pack unit is set so as to have a predetermined relationship with the recording position determined by the corresponding time management information.Type: GrantFiled: May 16, 2003Date of Patent: September 2, 2008Assignee: Sony CorporationInventors: Fumiyoshi Abe, Takuji Himeno, Toshinori Kouzai, Yonetaro Totsuka
-
Publication number: 20060155964Abstract: Methods and apparatus provide for disabling at least some data path processing circuits of a SIMD processing pipeline, in which the processing circuits are organized into a matrix of slices and stages, in response to one or more enable flags during a given cycle.Type: ApplicationFiled: January 13, 2005Publication date: July 13, 2006Inventor: Yonetaro Totsuka
-
Publication number: 20060153538Abstract: In an image data processing method of recording auxiliary data intended for splicing with the MPEG-2 technique to a recording medium, a VBV delay of an I or P picture is acquired from an data group led by the I or P picture and including a B picture, a VBV delay (VBV_delay_N) of a next picture is pre-acquired, the acquired VBV delay is recorded to an auxiliary recording area provided for each data group in order to record encoded image data to a predetermined recording area in a recording medium for each data group, and the pre-acquired VBV_delay_N is recorded to an auxiliary recording area for a next picture, provided correspondingly to a recording area for the next picture.Type: ApplicationFiled: July 2, 2003Publication date: July 13, 2006Inventors: Takuji Himeno, Fumiyoshi Abe, Hiroyasu Tsuchida, Toshinori Kouzai, Yonetaro Totsuka
-
Publication number: 20060101108Abstract: A method, an apparatus, and a computer program are provided to more efficiently generate a sticky bit in a Floating Point Design. Traditionally, separate ORing logic or OR trees were employed to compress the stick outputs of a normalization shifter into at least one sticky bit. However, this design has power consumption and area costs associated with it. To overcome these disadvantages, the OR trees of Leading Zero Counters (CLZs) are employed in conjunction with the Edge Vector logic of a Leading Sign Anticipator and an additional OR gate to determine the sticky bit.Type: ApplicationFiled: November 5, 2004Publication date: May 11, 2006Applicants: International Business Machines Corporation, Sony Computer Entertainment Inc.Inventors: Sang Dhong, Christian Jacobi, Silvia Mueller, Hwa-Joon Oh, Yonetaro Totsuka
-
Publication number: 20060053190Abstract: An apparatus, a method, and a computer program are provided for anticipating leading zeros for a Floating Point (FP) computation. Traditional leading zero anticipators (LZA) are typically very wide. To reduce the width of the LZA, it is subdivided to two smaller LZA that compute edge vectors for the most and least significant bits of intermediate resultant vectors. Therefore, a LZA can be easily folded to reduce the area requirement so as to increase the versatility of the LZA.Type: ApplicationFiled: September 9, 2004Publication date: March 9, 2006Applicants: International Business Machines Corporation, Sony Computer Entertainment Inc.Inventors: Sang Hoo Dhong, Christian Jacobi, Hwa-Joon Oh, Silvia Melitta Mueller, Yonetaro Totsuka
-
Publication number: 20050238331Abstract: The present invention applies to a video tape recorder that records HDTV (High Definition TeleVision) video signals, in particular, onto a magnetic tape, and records at least reproduction standard management information ETN in the order of pictures of video data to be reproduced and output in a main sector, and in the order of pictures of compressed video data in a subcode sector. Search data is recorded on the basis of time management information of video data at the time of decoding, while display data is recorded on the basis of time management information on reproduction and output of video data.Type: ApplicationFiled: May 16, 2003Publication date: October 27, 2005Inventors: Fumiyoshi Abe, Takuji Himeno, Toshinori Kouzai, Yonetaro Totsuka
-
Publication number: 20050238330Abstract: The present invention is particularly applied to a video tape recorder for recording a video signal of an HDTV (high-definition television) on a magnetic tape. In the video tape recorder, the recording position of the head of each pack unit is set so as to have a predetermined relationship with the recording position determined by the corresponding time management information.Type: ApplicationFiled: May 16, 2003Publication date: October 27, 2005Inventors: Fumiyoshi Abe, Takuji Himeno, Toshinori Kouzai, Yonetaro Totsuka
-
Publication number: 20040158756Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: ApplicationFiled: February 2, 2004Publication date: August 12, 2004Applicant: Renesas Technology CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
-
Patent number: 6715090Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: May 20, 1999Date of Patent: March 30, 2004Assignee: Renesas Technology CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
-
Patent number: 6640298Abstract: A branch prediction apparatus to minimize branch penalties in pipeline or concurrent processing of a sequence of instructions correctly predicts a pattern in which “branch taken” and “branch not taken” alternately appear. The apparatus includes a branch prediction table to keep one history bit and a 2-bit counter for each branch instruction, a prediction generator to output a value of the history bit when the counter has a value of 0 or 2 and to output a value obtained by reversing the history bit when the counter has a value of 1 or 3, and a counter controller which compares a result of branch with a value of the history bit. The counter controller sets 0 to the counter value when the result matches the value and adds one to the counter value when the result does not match the value and the counter value is other than 3.Type: GrantFiled: April 7, 2000Date of Patent: October 28, 2003Assignee: Hitachi, Ltd.Inventors: Yonetaro Totsuka, Yoshio Miki
-
Patent number: 6327605Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.Type: GrantFiled: March 19, 2001Date of Patent: December 4, 2001Assignee: Hitachi, Ltd.Inventors: Fumio Arakawa, Norio Nakagawa, Tetsuya Yamada, Yonetaro Totsuka
-
Publication number: 20010011291Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.Type: ApplicationFiled: March 19, 2001Publication date: August 2, 2001Inventors: Fumio Arakawa, Norio Nakagawa, Tetsuya Yamada, Yonetaro Totsuka
-
Patent number: 6243732Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.Type: GrantFiled: January 7, 2000Date of Patent: June 5, 2001Assignee: Hitachi, Ltd.Inventors: Fumio Arakawa, Norio Nakagawa, Tetsuya Yamada, Yonetaro Totsuka
-
Patent number: 6044450Abstract: Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit.Type: GrantFiled: March 27, 1997Date of Patent: March 28, 2000Assignee: Hitachi, Ltd.Inventors: Yuji Tsushima, Yoshikazu Tanaka, Yoshiko Tamaki, Masanao Ito, Kentaro Shimada, Yonetaro Totsuka, Shigeo Nagashima
-
Patent number: 6038582Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.Type: GrantFiled: October 15, 1997Date of Patent: March 14, 2000Assignee: Hitachi, Ltd.Inventors: Fumio Arakawa, Norio Nakagawa, Tetsuya Yamada, Yonetaro Totsuka