Abstract: In establishment of a general-purpose artificial intelligence system, the machine simulates similarity, repeatability and adjacency of information, and stores the demand, award/penalty and emotion symbols together with related low-level features as a preset relation network. When the machine encounters input information, the machine iteratively identifies low-level features in the input information and stores them in a memory according to a simultaneous storage method. With the low-level features as nodes and the similarity, repeatability and adjacency relations between nodes as connection relations, the machine establish relations between the low-level features and the demand, award/penalty and emotion symbols to extend the relation network.

Abstract: In establishment of a general-purpose artificial intelligence system, the machine simulates similarity, repeatability and adjacency of information, and stores the demand, award/penalty and emotion symbols together with related low-level features as a preset relation network. When the machine encounters input information, the machine iteratively identifies low-level features in the input information and stores them in a memory according to a simultaneous storage method. With the low-level features as nodes and the similarity, repeatability and adjacency relations between nodes as connection relations, the machine establish relations between the low-level features and the demand, award/penalty and emotion symbols to extend the relation network.

Abstract: A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.

Abstract: A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.

Abstract: A power-on reset circuit for use in an integrated circuit. The power-on reset circuit comprises an inverter, a switch means, and a number of diode-connected transistors. The switch means having a control terminal connected to an output terminal of the inverter is coupled between a power supply and an input terminal of the inverter. The diode-connected transistors are connected in series between the power supply and the input terminal of the inverter. The power-on reset circuit also comprises another diode-connected transistor connected between the input terminal of the inverter and a circuit ground. This diode-connected transistor is preferably connected in inverse series with the remaining diode-connected transistors.