Abstract: A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. The one semiconductor device may include an address output circuit configured to output the addresses. The one semiconductor device may include an encryption circuit configured to output the encrypted data based on normal data and the addresses. The one semiconductor device may include a decryption circuit configured to output the normal data based on the addresses and the encrypted data.

Abstract: A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. The one semiconductor device may include an address output circuit configured to output the addresses. The one semiconductor device may include an encryption circuit configured to output the encrypted data based on normal data and the addresses. The one semiconductor device may include a decryption circuit configured to output the normal data based on the addresses and the encrypted data.

Abstract: The semiconductor memory device includes a cell array unit comprising a plurality of cell mats; a column decoder suitable for outputting a plurality of column selection signals based on a column address to a plurality of column selection lines, respectively, during a normal operation, and for applying a signal having a first logic level to the plurality of column selection lines during a test operation; and a line defect detection circuit suitable for detecting whether a defect is present in the plurality of column selection lines in response to signals of the plurality of column selection lines, and outputting a defect detection signal based on the detection result, during the test operation.

Abstract: A semiconductor apparatus includes a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a PMOS transistor and an NMOS transistor in response to a detection enable signal, a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages, a reference voltage generation circuit configured to generate a reference voltage in response to the detection code, an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage, and an internal circuit configured to operate by receiving the internal voltage.

Abstract: A memory system includes a memory device configured to store input data with a first time interval that is adjusted in response to a write command and a precharge command; and a controller configured to generate the write command and the precharge command, and to control the memory device, wherein the controller sets a change rate of the first time interval according to a temperature of the memory device, and adjusts a time interval between the write command and the precharge command on a basis of the set change rate and the temperature of the memory device.

Abstract: A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. The one semiconductor device may include an address output circuit configured to output the addresses. The one semiconductor device may include an encryption circuit configured to output the encrypted data based on normal data and the addresses. The one semiconductor device may include a decryption circuit configured to output the normal data based on the addresses and the encrypted data.

Abstract: A semiconductor apparatus includes a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a PMOS transistor and an NMOS transistor in response to a detection enable signal, a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages, a reference voltage generation circuit configured to generate a reference voltage in response to the detection code, an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage, and an internal circuit configured to operate by receiving the internal voltage.

Abstract: A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an LIO line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (I/O) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information. If the page-size information is the first information, the LIO line switching circuit generates the first and second selection signals using a row address, and if the page-size information is the second information, the LIO line switching circuit generates the first and second selection signals using a column address.

Abstract: A data output device may include a driving control, a voltage supply unit, and an output driving unit. The driving control unit outputs a pull-up control signal and a pull-down control signal in response to a logic value of data when an output enable signal is activated. The voltage supply unit generates a driving voltage lower than a supply voltage. The output driving unit is driven in response to the driving voltage, and controls an amplitude and a slew rate of a voltage supplied to a global line according to the pull-up control signal and the pull-down control signal.

Abstract: A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks.

Abstract: A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.

Abstract: The semiconductor device includes a first channel region suitable for including a first pad region and a first core region and receiving a first power signal through a first power line, a second channel region suitable for including a second pad region and a second core region and receiving the first power signal through a second power line, and a switch unit suitable for electrically disconnecting the second power line from a first power stabilization unit if a predetermined operation of the first channel region is performed and electrically disconnecting the first power line from the first power stabilization unit if the predetermined operation of the second channel region is performed.

Abstract: A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks.

Abstract: The semiconductor device includes a first channel region suitable for including a first pad region and a first core region and receiving a first power signal through a first power line, a second channel region suitable for including a second pad region and a second core region and receiving the first power signal through a second power line, and a switch unit suitable for electrically disconnecting the second power line from a first power stabilization unit if a predetermined operation of the first channel region is performed and electrically disconnecting the first power line from the first power stabilization unit if the predetermined operation of the second channel region is performed.

Abstract: A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.

Abstract: A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an LIO line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (I/O) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information. If the page-size information is the first information, the LIO line switching circuit generates the first and second selection signals using a row address, and if the page-size information is the second information, the LIO line switching circuit generates the first and second selection signals using a column address.

Abstract: Command decoders are provided. The command decoder includes an input buffer configured for buffering and receiving command address signals having address information and command information at first, second, third, and fourth edges of a clock pulse signal according to a reference voltage, a latch circuit configured for latching the command address signals output from the input buffer at the first and third edges of the clock pulse signal to generate and output latched signals, a first command generator configured for decoding the latched signals output from the latch circuit at the first edge of the clock pulse signal to generate and output a first internal command, and a second command generator configured for decoding the latched signals output from the latch circuit at the third edge of the clock pulse signal to generate and output a second internal command.

Abstract: A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer groups and the respective I/O lines in response to a normal control clock signal.

Abstract: An integrated circuit includes: a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and a fail address storage unit configured to store the fail address.

Abstract: A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group, a coupling circuit configured to couple an output terminal and an inverse output terminal of a selected page buffer of the first page buffer group to a first local I/O line and a first inverse local I/O line, respectively, or an output terminal and an inverse output terminal of a selected page buffer of the second page buffer group to a second local I/O line and a second inverse local I/O line, respectively, in response to a column select signal, and a sense amplifier configured to detect a voltage difference between the first local I/O line and the first inverse local I/O line or between the second local I/O line and the second inverse local I/O line.