Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

Abstract: The present invention includes a class-E power amplifier, comprising a driver stage (DS) including a first power amplifier with transistors, to which an input signal is inputted; a main stage (MS), including a second power amplifier with transistors, whose input is connected to the output of the DS; and a first LC resonator whose one end is connected to the output of the DS and the other end to the ground as an AC equivalent circuit and a second LC resonator whose one end is connected to the input of the MS and the other end to the ground as an AC equivalent circuit. In accordance with the present invention, as the voltage stress is reduced on the CMOS class-E power amplifier, the application of the high power supply voltage may be allowed and therefore the load impedance may be high while the same efficiency is maintained.

Abstract: The present invention includes a class-E power amplifier, comprising a driver stage (DS) including a first power amplifier with transistors, to which an input signal is inputted; a main stage (MS), including a second power amplifier with transistors, whose input is connected to the output of the DS; and a first LC resonator whose one end is connected to the output of the DS and the other end to the ground as an AC equivalent circuit and a second LC resonator whose one end is connected to the input of the MS and the other end to the ground as an AC equivalent circuit. In accordance with the present invention, as the voltage stress is reduced on the CMOS class-E power amplifier, the application of the high power supply voltage may be allowed and therefore the load impedance may be high while the same efficiency is maintained.

Abstract: The present invention provides an ashing method using rapid heat transfer under high pressure. The present method, applicable to all photoresist ashing processes, can rapidly remove hardened photoresists without popping at the ashing step by baking high dose ion implanted silicon substrate on a hot plate, enhancing the ashing quantity, by drastically reducing the ashing process time, while allowing conventional equipments to be used further. The present method comprises an in situ baking step, wherein a silicon substrate is baked for a predetermined time period under a pressure of 10 Torr or more while it is placed on a hot plate; a vacuumizing step, wherein a stable vacuum status is achieved while the silicon substrate is placed on the hot plate; a gas processing step, wherein selected reaction gas is introduced into a reaction chamber; and an ashing step, wherein plasma is generated until almost all of the photoresists are removed.