Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and a plurality bit lines to corresponding rows and columns of resistive memory cells in the array. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance associated therewith is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance associated therewith, which is greater than the first parasitic resistance.

Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.

Abstract: Provided is a pharmaceutical composition including quercetin-3-O-?-D-xylopyranoside for preventing or treating a liver disease. Since the composition has an effect on inhibiting alcohol-induced accumulation of triglycerides in the blood and liver, having no toxicity and without affecting feed intake, body weight, organ weight, and the like, the composition of the present invention may be efficiently utilized as a pharmaceutical composition for preventing and treating a liver disease such as steatosis, hepatitis, hepatic fibrosis, and cirrhosis or a health functional food for preventing or alleviating a liver disease such as steatosis, hepatitis, hepatic fibrosis, and cirrhosis.

Abstract: Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.

Abstract: A hydraulic actuator to which a limit-adjustable mechanical lock device is applied, comprising: a housing having a first hole; side covers coupled at both sides of the housing, and having holder insertion holes formed to be opened toward the first hole side of the housing, and plugs; a first holder of which one side of the outer peripheral surface is inserted into the holder insertion hole at the plug side of the side cover by screw coupling; a second holder fitted and coupled to the inner peripheral surface of the side cover and having one end thereof screw-coupled to the second hole of the first holder; a locking means into which a rod is inserted so as to be movable in an axial direction at a predetermined distance across the second hole of the first holder and the third hole of the second holder.

Abstract: Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

Abstract: A display device is provided. The display device includes a display panel and an upper container in which the display panel is disposed. The upper container includes a cover portion which covers top edges of the display panel, a side wall which extends from the cover portion to cover a side of the display panel, and apertures defined in the side wall of the upper container, the apertures exposing the display panel to outside the display device at the side wall.

Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.

Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phase-change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.

Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Abstract: A memory device includes: a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells includes a switching element, and a data storage element connected to the switching element, wherein the data storage element includes a phase change material; and a memory controller configured to perform a control operation with respect to a first memory cell of the plurality of memory cells by inputting an operating current to the first memory cell, and inputting a compensation current flowing from the data storage element to the switching element in the first memory cell before or after inputting the operating current to the first memory cell.

Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.

Abstract: Disclosed is a refill case detachably accommodated in a cosmetic compact, the refill case including: a main body being configured such that an upper portion thereof is open, and including an inner wall providing an accommodation space in the main body, and an outer wall provided at an outer side of the main body with a predetermined gap between the inner wall and the outer wall; and a mesh fabric cover including a cylindrical vertical extension portion tightly inserted in the gap, a rim portion extending from an upper end of the vertical extension portion in an inward direction, and a mesh fabric configured such that upper and lower surfaces thereof are interposed between the upper end of the vertical extension portion and an outer edge the rim portion along an edge thereof to be integrally provided, thereby covering an upper portion of the accommodation space.

Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.

Abstract: A secondary battery is provided. The secondary battery may include an electrode assembly; a pouch including a sealing portion along outer edges thereof and configured to accommodate and seal the electrode assembly; an electrode lead inserted through the sealing portion and connected to the electrode assembly, the electrode lead including a first vent hole opened toward the electrode assembly; and lead films disposed between the electrode lead and the sealing portion of the pouch, the lead films including second vent holes opened toward the electrode assembly. The second vent holes may overlap the first vent hole to form a path penetrating the lead films and the electrode lead.

Abstract: A nonvolatile memory device includes memory banks and write block circuits. Each of the memory banks includes an array of memory cells. Each of the memory cells is disposed in a region of the memory banks in which bit lines and word lines intersect. The write block circuits are connected to the memory banks. Each of the write block circuits includes write drivers, that are each connected to the bit lines. The write block circuits provide a write current of the memory cells to the bit lines. A total number of write block circuits is used to determine the number of memory banks that are simultaneously provided with a write command from a host. A total number of write drivers that are activated is based on a predetermined reference value.

Abstract: A memory device having a resistance change material and an operating method of the memory device are provided. A memory device includes a memory cell array including first and second resistive memory cells, which store different data according to the change of their resistance; a buffer including first and second storage regions corresponding to the first and second resistive memory cells, respectively; and a control circuit receiving program data to be programmed to the memory cell array, comparing first data stored in the first storage region and second data stored in the first resistive memory cell, and as a result of the comparison determining one of the first and second storage regions as a storage region to which to write the program data.

Abstract: The present invention relates to a compact for cosmetics comprising an upper case, a lower case rotatably coupled to the upper case and a refill case detachably received in the lower case, wherein the refill case comprises a case mainbody where contents for cosmetics are received; a case cover which opens and closes the case mainbody; and a mesh screen cover having a border rim part which is received in the case mainbody to be tightly received within a wall of the mainbody, and a high elasticity mesh screen which has a border area supported by the border rim part to extend inwardly so as to cover the contents for cosmetics from an outside. Accordingly, expanded space is provided for receiving contents for cosmetics, the contents for cosmetics is prevented from flowing out of the refill case by the high elasticity mesh screen covering the contents for cosmetics, and the contents for cosmetics is prevented from being directly exposed to the outside thus decreasing vaporization when the case is open.