Abstract: A semiconductor device having a three-dimensional (3D) channel region and a method of manufacturing the same. More particularly, in the semiconductor device and method of manufacturing a vertically extended path of a lower surface of a gate is configured in 3D such that a vertically extended path of a channel region is also configured in 3D.

Abstract: A semiconductor device includes a source region disposed in a substrate and having a first conductivity type, a drain region disposed in the substrate and having the first conductivity type, a first drift region having the first conductivity type and extending in a channel length direction between the source and drain regions, a second drift region having a second conductivity type and extending parallel to the first drift region, a field plate region disposed in an upper portion of the second drift region, an auxiliary electrode disposed in an upper portion of the field plate region, and a gate electrode disposed on the substrate and electrically connected with the auxiliary electrode. Such devices can reduce the specific on-resistance while also reducing electric field concentrations at the edge portions of the gate electrode, and the breakdown voltage of the device can therefore be significantly improved.

Abstract: A semiconductor device includes a source region disposed in a substrate and having a first conductivity type, a drain region disposed in the substrate and having the first conductivity type, a first drift region having the first conductivity type and extending in a channel length direction between the source and drain regions, a second drift region having a second conductivity type and extending parallel to the first drift region, a field plate region disposed in an upper portion of the second drift region, an auxiliary electrode disposed in an upper portion of the field plate region, and a gate electrode disposed on the substrate and electrically connected with the auxiliary electrode. Such devices can reduce the specific on-resistance while also reducing electric field concentrations at the edge portions of the gate electrode, and the breakdown voltage of the device can therefore be significantly improved.

Abstract: An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced.

Abstract: An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced.

Abstract: Semiconductor devices and methods for fabricating the same are disclosed. The semiconductor device includes gate electrodes having sidewall spacers on a semiconductor substrate, double diffusion drain regions in the semiconductor substrate adjacent to the sidewall spacers, double diffusion junction regions aligned with the gate electrodes, and source/drain regions in the double diffusion junction regions.

Abstract: Semiconductor devices and methods for fabricating the same are disclosed. The semiconductor device includes gate electrodes having sidewall spacers on a semiconductor substrate, double diffusion drain regions in the semiconductor substrate adjacent to the sidewall spacers, double diffusion junction regions aligned with the gate electrodes, and source/drain regions in the double diffusion junction regions.

Abstract: A flash memory device has a single-poly structure. A method for manufacturing the flash device includes forming an oxide layer over a semiconductor substrate having a P-well region or N-well region. A shallow trench isolation (STI) may be formed in the semiconductor substrate and the oxide layer. A drift region may be formed by injecting a dopant into a part of the P-well region or N-well region. A gate oxide layer and a poly-silicon layer may be formed over the well region, the drift region, and the STI. A control gate pattern may be formed by patterning the gate oxide layer and the poly-silicon layer. A source region and a drain region may be formed on opposite sides of the control gate pattern. A silicon nitride layer may be deposited over the control gate pattern and etching the silicon nitride layer to form a spacer around a sidewall of the control gate pattern.

Abstract: Embodiments relate to a high voltage semiconductor device. The device includes a substrate having impurities of a first conductivity and having a first surface and a second surface, a gate electrode over the first surface, an LDD region having low concentration impurities of a second conductivity doped in the substrate at a first side of the gate electrode, a drain region having high concentration impurities of the second conductivity doped in the LDD region, a source region having high concentration impurities of the second conductivity doped in the substrate at a second side of the gate electrode, and spacers formed at sidewalls of the gate electrode. The first surface is higher than the second surface, and the source and LDD regions are at least partially formed in a region at the second surface. A bottom side of one of the spacers directly contacts the LLD region.

Abstract: Disclosed is a semiconductor device, and more particularly, a manufacturing method of a high voltage semiconductor device. The method includes: forming a semiconductor substrate having a key area for an alignment key, a low voltage area for a low voltage device, and a high voltage area for a high voltage device; forming an oxide film on the substrate; and forming an insulating film on the oxide film. After removing the insulating film, the method includes forming a plurality of shallow trench isolations (STI's) in the areas of the substrate; forming a nitride layer on the substrate and on STIs; sequentially forming a plurality of wells and drift areas by implanting an impurity ion into the high voltage area; and sequentially forming the plurality of wells and the drift areas by implanting an impurity ion into the low voltage area. A system on chip (SOC) process may thus be simplified.

Abstract: Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an oxide film on a silicon substrate in which an upper metal pad may be formed and a second oxide film may be formed by performing only deposition on the first oxide film. A thickness of the first oxide film may be set to be above 5 k?. A first passivation layer may be formed by planarizing the first and second oxide films. In the planarizing process, a thickness of the first passivation layer may be 4 k?. A second passivation layer of a nitride film may be formed on the first passivation layer and the first and second passivations may be selectively etched so as to expose the upper metal pad.

Abstract: A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions.

Abstract: A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions.

Abstract: A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an opening in a high voltage region. An oxide layer is deposited over the substrate and anisotropically etched to remain only on sidewalls of the opening. A first gate oxide layer is formed on the substrate in the opening, and the nitride layer is removed. Then a second gate oxide layer is formed over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer. Gate electrodes are then formed in the high voltage region and the low voltage region.

Abstract: Embodiments relate to the lowered reliability of a device due to deterioration caused by the concentration of an electric field in the top corner of an STI. To solve the reliability problem, the STI top corners have a local oxidation of silicon, the top corners of the STI are rounded, and the STI steps are increased in a semiconductor device fabricated according to embodiments. Embodiments relate to an STI in high and low voltage regions of a semiconductor device which can be fabricated by providing a semiconductor substrate having a shallow trench isolation structure, a high voltage region and a low voltage region. A capping layer is formed over the entire surface of the top of the high voltage region and the low voltage region, including the shallow trench isolation structure. A photoresist pattern is formed over the top of the capping layer to expose the high voltage region, including a portion of the shallow trench isolation structure formed within the high voltage region.

Abstract: A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an opening in a high voltage region. An oxide layer is deposited over the substrate and anisotropically etched to remain only on sidewalls of the opening. A first gate oxide layer is formed on the substrate in the opening, and the nitride layer is removed. Then a second gate oxide layer is formed over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer. Gate electrodes are then formed in the high voltage region and the low voltage region.

Abstract: Disclosed is a semiconductor device, and more particularly, a manufacturing method of a high voltage semiconductor device. The method includes: forming a semiconductor substrate having a key area for an alignment key, a low voltage area for a low voltage device, and a high voltage area for a high voltage device; forming an oxide film on the substrate; and forming an insulating film on the oxide film. After removing the insulating film, the method includes forming a plurality of shallow trench isolations (STI's) in the areas of the substrate; forming a nitride layer on the substrate and on STIs; sequentially forming a plurality of wells and drift areas by implanting an impurity ion into the high voltage area; and sequentially forming the plurality of wells and the drift areas by implanting an impurity ion into the low voltage area. A system on chip (SOC) process may thus be simplified.

Abstract: A planar-type semiconductor device including a plurality of device isolation areas defining an active area formed over a semiconductor substrate; at least one drift area formed in the semiconductor substrate; a well region formed in the semiconductor substrate; a gate pattern formed over the semiconductor substrate and between the plurality of device isolation areas; a pair of source regions and a drain area formed in the semiconductor substrate adjacent sides of the gate pattern; at least one drift region formed in the well region; a drain region formed in the drift region; and a silicide layer formed over the source regions, the drain region, and partially over the gate pattern.

Abstract: A flash memory device has a single-poly structure. A method for manufacturing the flash device includes forming an oxide layer over a semiconductor substrate having a P-well region or N-well region. A shallow trench isolation (STI) may be formed in the semiconductor substrate and the oxide layer. A drift region may be formed by injecting a dopant into a part of the P-well region or N-well region. A gate oxide layer and a poly-silicon layer may be formed over the well region, the drift region, and the STI. A control gate pattern may be formed by patterning the gate oxide layer and the poly-silicon layer. A source region and a drain region may be formed on opposite sides of the control gate pattern. A silicon nitride layer may be deposited over the control gate pattern and etching the silicon nitride layer to form a spacer around a sidewall of the control gate pattern.

Abstract: A method for forming gate oxide layers of a semiconductor device including defining a first, a second, and a third device region by forming device isolation regions on a semiconductor substrate. The method also includes forming a sacrificing dielectric layer on the substrate, removing the sacrificing dielectric layer on the first device region by selective etching, and forming a first gate oxide layer by oxidizing the first device region. The method further includes removing the sacrificing dielectric layer on the second and third device regions, forming a second gate oxide layer on the second and third device region by oxidizing the substrate, forming a photoresist pattern exposing the third device region and covering the first and second device regions, and forming a third gate oxide layer by oxidizing the third device region.