Abstract: A buffer unit for temporarily storing a substrate includes a housing having a space for storing a substrate therein, one or more slots disposed within the housing for placing a substrate thereon, and a holding unit disposed at a bottom portion of the housing, having a flat and non-inclined top surface, and comprising a built-in wireless charging module. A substrate type sensor is stored at the holding unit.

Abstract: The present invention relates to a method of improving the corrosion resistance of a metal substrate surface using an oxygen reduction catalyst, which may improve the corrosion resistance of the metal substrate surface by coating the metal substrate surface with the oxygen reduction catalyst so that the metal substrate surface is changed to a passive state through the action of the oxygen reduction catalyst in an environment in which a stable oxide layer is not spontaneously formed on the metal substrate surface. The present invention has an advantage in that it can dramatically improve the corrosion resistance of the metal substrate under a corrosive environment by allowing a recoverable oxide layer to be formed on the metal substrate surface through the action of the oxygen reduction catalyst, applied to the surface, even in an environment in which an oxide layer is not spontaneously formed on the metal substrate.

Abstract: A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

Abstract: A semiconductor device may include a plurality of chips and a test pad. The plurality of chips may check parity bits of a plurality of pattern signals activated in units of specific bits and store test result signals generated by the checking of the parity bits. The plurality of chips may output an error detection signal when an error is detected from any of the test result signals. The test pad may output the error detection signal received from the plurality of chips to an external part. The plurality of chips may be commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal s output through the test pad.

Abstract: A semiconductor device includes a counter configured to count a refresh signal and output a counting signal. The semiconductor device may include a mode control circuit configured to receive a first mode signal for controlling a refresh cycle and a second mode signal for constantly controlling a refresh cycle, in correspondence to error correction code information, configured to output an advanced refresh signal in which the refresh cycle is adjusted, by controlling the counting signal depending on the first mode signal, and configured to output a smart refresh signal which has a constant refresh cycle, in correspondence to the second mode signal. The semiconductor device may include a refresh control circuit configured to output a bank address for performing a refresh operation that is set in correspondence to the advanced refresh signal and the smart refresh signal, to a bank.

Abstract: A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

Abstract: A semiconductor device may include a plurality of chips and a test pad. The plurality of chips may check parity bits of a plurality of pattern signals activated in units of specific bits and store test result signals generated by the checking of the parity bits. The plurality of chips may output an error detection signal when an error is detected from any of the test result signals. The test pad may output the error detection signal received from the plurality of chips to an external part. The plurality of chips may be commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal s output through the test pad.

Abstract: A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

Abstract: A semiconductor device includes a counter configured to count a refresh signal and output a counting signal. The semiconductor device may include a mode control circuit configured to receive a first mode signal for controlling a refresh cycle and a second mode signal for constantly controlling a refresh cycle, in correspondence to error correction code information, configured to output an advanced refresh signal in which the refresh cycle is adjusted, by controlling the counting signal depending on the first mode signal, and configured to output a smart refresh signal which has a constant refresh cycle, in correspondence to the second mode signal. The semiconductor device may include a refresh control circuit configured to output a bank address for performing a refresh operation that is set in correspondence to the advanced refresh signal and the smart refresh signal, to a bank.

Abstract: A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

Abstract: A memory apparatus includes a first memory bank, a second memory bank, a row decoder and repair circuit, and an input/output driver controller. The row decoder and repair circuit is coupled to the first and second memory banks in common. The row decoder and repair circuit generates a shared repair signal according to whether a word line disposed in a first memory bank is replaced with a word line disposed in a second memory bank. The input/output driver controller allows read or write operations for one of the first and second memory banks to be performed based on the shared repair signal and an operation signal.

Abstract: A file sharing system may comprise a server configured to store a sharing file having one or more versions and an identifier of the sharing file, receive the sharing file and the identifier of the sharing file from one or more devices, and determine a version of the received sharing file corresponding to the identifier of the sharing file by using a hash value of the sharing file and a time editing the sharing file. A file sharing method may comprise sending, by a server, one or more messages associated with a sharing file to one or more devices which store the sharing file and have authorization to access the messages associated with the sharing file.

Abstract: In a semiconductor integrated circuit layout, a power voltage line for supplying a power voltage to the semiconductor integrated circuit is connected to an active area where an NMOS transistor and/or a PMOS transistor are formed, by using the active area. An active area is formed between an active area where the power voltage line and/or a ground voltage line are formed and the active area where the NMOS transistor and/or the PMOS transistor are formed. In this manner, the active area where the power voltage line and/or the ground voltage line are formed and the active area where the NMOS transistor and/or the PMOS transistor are formed are connected.

Abstract: A method and apparatus for converting a resolution of a document to be transmitted at a high rate is disclosed. Horizontal converting section reduces or magnifies an input signal in accordance with the horizontal resolution specified by both a conversion magnification signal and a reduction/magnification mode signal in response to reference clock signals, and provides a horizontal conversion signal horizontally converted and a horizontal dot signal. Vertical converting section reduces or magnifies the horizontal conversion signal from the horizontal converting section in accordance with the vertical resolution specified by the conversion magnification signal on the basis of a line start signal, the conversion magnification signal and the mode signal, and provides a vertical conversion signal. Address generating section provides an address signal on the basis of the line start signal.