Abstract: A display device is provided. The display device includes a substrate, a first electrode, a second electrode, and third electrode spaced apart from each other in a first direction on the substrate, a repair line spaced apart from the first to third electrodes in the first direction on the substrate, a repair connection portion connecting the third electrode and the repair line, and light emitting elements on respective ones of the first to third electrodes and spaced apart from each other.

Abstract: A display device includes: first and second display panels adjacent to each other along one direction, wherein: each of the first and second display panels includes a substrate, and a display portion on the substrate and includes a plurality of pixels including a pixel circuit layer on the substrate, at least one transistor, a display element layer on the pixel circuit layer, and at least one light emitting element emitting light; the substrate of the first display panel and the substrate of the second display panel are engaged with each other in a plan view and a cross-sectional view; the display portion of the first display panel and the display portion of the second display panel are engaged with each other in a plan view and a cross-sectional view; and a boundary between the display portion of the first display panel and the display portion of the second display panel.

Abstract: A display device comprises a substrate, a via layer disposed on the substrate, a first electrode and a second electrode disposed on the via layer and spaced apart from each other, a third electrode that overlaps a region between the first electrode and the second electrode in a thickness direction, and light-emitting elements disposed on the first electrode and the second electrode, wherein the third electrode overlaps portions of the first electrode and the second electrode in the thickness direction.

Abstract: A tiled display device includes a plurality of display devices adjacent to each other, each of the display devices including a plurality of first pixels and a plurality of second pixels, and a boundary area in which at least one side of each of the display devices is adjacent to a side of another display device and a main area other than the boundary area, wherein the first pixels are in the main area, the second pixels are in the boundary area, each of the first pixels and the second pixels includes a plurality of sub pixels, and each of the sub pixels of the second pixels includes a plurality of partial pixels.

Abstract: The present disclosure relates to a display device. The display device includes a substrate. The substrate includes a first display area, a second display area, a plurality of first pixels, a plurality of second pixels, and a plurality of diffraction patterns. The plurality of first pixels are disposed on the first display area. The plurality of second pixels are disposed on the second display area. The plurality of diffraction patterns are disposed on the second pixels When viewed in a plane orientation, an array density of the first pixels disposed in the first display area is greater than an array density of the second pixels disposed in the second display area.

Abstract: A display device includes a power generator to supply a driving voltage to the display and a controller to control the display and the power generator and to generate a power control signal. The power generator includes a DC-DC converter and bypass cut-off logic. The DC-DC converter receives an input power voltage and the power control signal, selectively boosts the input power voltage based on the power control signal, and generates the driving voltage. The bypass cut-off logic selectively cuts off supply of the input power voltage to the DC-DC converter based on the power control signal.

Abstract: A display device includes a power generator to supply a driving voltage to the display and a controller to control the display and the power generator and to generate a power control signal. The power generator includes a DC-DC converter and bypass cut-off logic. The DC-DC converter receives an input power voltage and the power control signal, selectively boosts the input power voltage based on the power control signal, and generates the driving voltage. The bypass cut-off logic selectively cuts off supply of the input power voltage to the DC-DC converter based on the power control signal.

Abstract: A display apparatus includes a timing controller configured to generate a single clock control signal comprising a plurality of ON-control pulses and a plurality of OFF-control pulses, a gate clock generator configured to generate a plurality of clock signals based on the single clock control signal, ON-periods of the plurality of clock signals starting in response to an ON-control pulse among the ON-control pulses and OFF-periods of the plurality of clock signals starting in response to an OFF-control pulse among the OFF-control pulses, a gate driver comprising a plurality of shift registers which generates a plurality of gate signals based on the plurality of clock signals, and a display panel comprising a display area in which a plurality of pixels is arranged and a peripheral area in which the plurality of shift registers is arranged.

Abstract: A display device includes a power generator to supply a driving voltage to the display and a controller to control the display and the power generator and to generate a power control signal. The power generator includes a DC-DC converter and bypass cut-off logic. The DC-DC converter receives an input power voltage and the power control signal, selectively boosts the input power voltage based on the power control signal, and generates the driving voltage. The bypass cut-off logic selectively cuts off supply of the input power voltage to the DC-DC converter based on the power control signal.

Abstract: A voltage generator includes: a transforming unit to transform an input voltage into an output voltage in response to a switching signal; a feedback voltage controller to compare the output voltage with a reference voltage when a start signal is activated, and to output a feedback voltage corresponding to the comparison of the output voltage with the reference voltage; and a power controller to compare the feedback voltage with the reference voltage, and to output the switching signal corresponding to the comparison of the feedback voltage with the reference voltage.

Abstract: A display apparatus includes a timing controller configured to generate a single clock control signal comprising a plurality of ON-control pulses and a plurality of OFF-control pulses, a gate clock generator configured to generate a plurality of clock signals based on the single clock control signal, ON-periods of the plurality of clock signals starting in response to an ON-control pulse among the ON-control pulses and OFF-periods of the plurality of clock signals starting in response to an OFF-control pulse among the OFF-control pulses, a gate driver comprising a plurality of shift registers which generates a plurality of gate signals based on the plurality of clock signals, and a display panel comprising a display area in which a plurality of pixels is arranged and a peripheral area in which the plurality of shift registers is arranged.

Abstract: A display apparatus includes a timing controller configured to generate a single clock control signal comprising a plurality of ON-control pulses and a plurality of OFF-control pulses, a gate clock generator configured to generate a plurality of clock signals based on the single clock control signal, ON-periods of the plurality of clock signals starting in response to an ON-control pulse among the ON-control pulses and OFF-periods of the plurality of clock signals starting in response to an OFF-control pulse among the OFF-control pulses, a gate driver comprising a plurality of shift registers which generates a plurality of gate signals based on the plurality of clock signals, and a display panel comprising a display area in which a plurality of pixels is arranged and a peripheral area in which the plurality of shift registers is arranged.

Abstract: A method of controlling an output voltage of an apparatus is provided. The method includes comparing an input voltage of the apparatus with a reference voltage, activating the output voltage when the input voltage is greater than or equal to the reference voltage, comparing the input voltage with a first low limit voltage or a first high limit voltage, comparing a first elapse time with a reference time when the input voltage is less than or equal to the first low limit voltage, comparing a second elapse time with the reference time when the input voltage is greater than or equal to the first high limit voltage, and deactivating the output voltage when the first elapse time or the second elapse time is longer than or equal to the reference time.

Abstract: A display device includes a voltage generating unit configured to convert an input voltage into an analog driving voltage, a controller configured to receive input image data and an image control signal and generate custom image data and a data control signal, a source driving unit configured to receive the analog driving voltage and convert the custom image data into data voltages in response to the data control signal, a sensing unit configured to sense a load current, wherein the sensing unit is connected to one point on a path through which the input voltage is converted into the analog driving voltage to be provided to the source driving unit, and a display panel configured to receive the data voltages to display an image. The controller receives the sensed load current and generates a selection signal according to a first intensity of the load current.

Abstract: A display device includes a power generator to supply a driving voltage to the display and a controller to control the display and the power generator and to generate a power control signal. The power generator includes a DC-DC converter and bypass cut-off logic. The DC-DC converter receives an input power voltage and the power control signal, selectively boosts the input power voltage based on the power control signal, and generates the driving voltage. The bypass cut-off logic selectively cuts off supply of the input power voltage to the DC-DC converter based on the power control signal.

Abstract: A display device includes a display panel including data lines and scan lines coupled, a data driver configured to supply data voltages to the data lines based on digital video data, a scan driver configured to supply scan signals to the scan lines, a timing controller configured to select one of a normal mode and a self-refresh mode based on a panel self-refresh enable signal, where the data and scan drivers are driven by a first frame frequency in the normal mode and by a second frame frequency lower than the first frame frequency in the self-refresh mode, and a power supply source configured to supply driving voltages to the data and scan drivers and the timing controller and to transmits a direct current power voltage to an outside thereof, where a transmission of the direct current power voltage is blocked during a blank period in the self-refresh mode.

Abstract: A display apparatus includes a timing controller configured to generate a single clock control signal comprising a plurality of ON-control pulses and a plurality of OFF-control pulses, a gate clock generator configured to generate a plurality of clock signals based on the single clock control signal, ON-periods of the plurality of clock signals starting in response to an ON-control pulse among the ON-control pulses and OFF-periods of the plurality of clock signals starting in response to an OFF-control pulse among the OFF-control pulses, a gate driver comprising a plurality of shift registers which generates a plurality of gate signals based on the plurality of clock signals, and a display panel comprising a display area in which a plurality of pixels is arranged and a peripheral area in which the plurality of shift registers is arranged.

Abstract: A data lines driver includes a digital to analog converter configured to generate a normal data voltage based on a data signal, a buffer configured to buffer the normal data voltage and a power-on/reset part configured to generate an initial data voltage varying according to time and to selectively output either the initial data voltage or the normal data voltage.

Abstract: A voltage generator includes: a transforming unit to transform an input voltage into an output voltage in response to a switching signal; a feedback voltage controller to compare the output voltage with a reference voltage when a start signal is activated, and to output a feedback voltage corresponding to the comparison of the output voltage with the reference voltage; and a power controller to compare the feedback voltage with the reference voltage, and to output the switching signal corresponding to the comparison of the feedback voltage with the reference voltage.

Abstract: A display panel includes: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; a gate driver connected to the plurality of gate lines to apply a gate signal voltage; a data driver connected to the plurality of data lines to apply a data voltage and a negative data voltage; and a gate voltage divider for generating a gate signal voltage including gate-on and gate-off voltages to provided it to the gate driver. The gate voltage divider adjusts the gate-off voltage in accordance with a driving time of the display panel and a temperature of the display panel.