Abstract: Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable.

Abstract: Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable.

Abstract: The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.

Abstract: The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.

Abstract: The present invention provides a new way of improving yield in the physical design stage after detail routing, thereby optimizing integrated circuit (IC) layout designs for manufacturing. Embodied in an automatic layout yield improvement tool, the present invention replaces vias with redundant vias having redundant cut shapes or larger metal overlapping based on a novel geotopological approach to routed layout optimization. The geotopological approach enables the most favorable redundant via candidate to be selected for each modifiable regular via. The tool first checks all potential redundant vias in the order of yield favorableness. The modifiable regular via is then replaced by an ideal redundant via that does not introduce any design rule violations in the geotopological layout.