Patents by Inventor Yongbo JU

Yongbo JU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983109
    Abstract: An air freight rate data caching method and system. The method includes converting air freight rate data into a data format of a first-level cache, and storing same in the first-level cache; performing, on the basis of a flight origin city and a flight destination city, data fragmentation on the air freight rate data stored in the first-level cache so as to generate fragmented data; and storing the fragmented data, after same is validated, in a second-level cache. Each data node of the fragmented data cached in the second-level cache only includes part of the air freight rate data on which a fragmentation algorithm can be performed, and therefore, the horizontal expansion capacity of a cache system is improved relative to the case where cached data copies are all complete sets.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: May 14, 2024
    Assignee: TravelSky Technology Limited
    Inventors: Jinfang Du, Lingbin Meng, Wen Wen, Chunsheng Ju, Bing Liu, Yongbo Fei
  • Patent number: 11901375
    Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: February 13, 2024
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongbo Ju, Pengfei Cui, Jian Sun, Deshuai Wang, Xiangkai Shen, Jianbin Gao, Jiannan Wang, Guangshuai Wang
  • Patent number: 11588055
    Abstract: The present disclosure provides a thin-film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor of the present disclosure include a plurality of insulating layers, among which at least one insulating layer on the low temperature polysilicon layer comprises organic material, so vias could be formed in the organic material by an exposing and developing process, thereby effectively avoiding the over-etching problem of the low temperature polycrystalline silicon layer caused by dry etching process. By adopting the method for manufacturing the film transistors of the present disclosure, the contact area and uniformity of the drain electrode and the low temperature polysilicon material layer can be increased; the conductivity can be improved; and the production cycle of products can be greatly reduced and thereby improving the equipment capacity.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 21, 2023
    Assignees: ORDOS YUANGSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Liu, Yongbo Ju, Xikang Jin, Zhimin Wang, Jianbin Gao, Xiaoguang Chen, Xinbo Zhou, Jianjun Chen
  • Publication number: 20220367530
    Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
    Type: Application
    Filed: April 13, 2021
    Publication date: November 17, 2022
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongbo JU, Pengfei CUI, Jian SUN, Deshuai WANG, Xiangkai SHEN, Jianbin GAO, Jiannan WANG, Guangshuai WANG
  • Publication number: 20210328073
    Abstract: The present disclosure provides a thin-film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor of the present disclosure include a plurality of insulating layers, among which at least one insulating layer on the low temperature polysilicon layer comprises organic material, so vias could be formed in the organic material by an exposing and developing process, thereby effectively avoiding the over-etching problem of the low temperature polycrystalline silicon layer caused by dry etching process. By adopting the method for manufacturing the film transistors of the present disclosure, the contact area and uniformity of the drain electrode and the low temperature polysilicon material layer can be increased; the conductivity can be improved; and the production cycle of products can be greatly reduced and thereby improving the equipment capacity.
    Type: Application
    Filed: September 25, 2018
    Publication date: October 21, 2021
    Inventors: Wei LIU, Yongbo JU, Xikang JIN, Zhimin WANG, Jianbin GAO, Xiaoguang CHEN, Xinbo ZHOU, Jianjun CHEN