Patents by Inventor Yong-Gill Lee

Yong-Gill Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7211467
    Abstract: A method for fabricating leadless packages with mold locking characteristics is disclosed. A provided leadless leadframe has a plurality of units in a matrix, each unit includes an improved die pad with a plurality of indentations, such as semi-vias in the sidewall thereof and a plurality of leads around the die pad. After chip attachment and electrical connection, a plurality of package bodies for semiconductor packages are individually formed on the corresponding units and covered the indentations in order to enhance the horizontal mold locking capability of the die pad. Using punching, connecting bars of the leadless leadframe are removed to isolate the leadless packages.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: May 1, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sang-Bae Park, Yong-Gill Lee, Hyung-Jun Park, Kyung-Soo Rho, Jin-Hee Won
  • Patent number: 7125747
    Abstract: A process for manufacturing a plurality of leadless semiconductor packages includes an electrically testing step to test encapsulated chips in a matrix of a leadless leadframe. Firstly, a leadless leadframe having at least a packaging matrix is provided. The packaging matrix defines a plurality of units and a plurality of cutting streets between the units. The leadless leadframe has a plurality of leads in the units and a plurality of connecting bars connecting the leads along the cutting streets. A plated metal layer is formed on the upper surfaces of the leads and the upper surfaces of the connecting bars. After die-attaching, wire-bonding connection, and encapsulation, the leadless leadframe is etched to remove the connecting bars, then two sawing steps are performed. During the first sawing step, the plated metal layer on the upper surface of the connecting bars is cut out to electrically isolate the leads.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: October 24, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yong-gill Lee, Hyung-Jun Park, Sang-Bae Park
  • Publication number: 20060199308
    Abstract: A process for manufacturing sawing type leadless semiconductor packages includes a post mold-curing step, which is performed after an encapsulant is formed and after connecting bars of a leadframe are removed. The connecting bars are formed between a plurality of package units of the leadframe to connect a plurality of leads in the package units. After die attachment and electrical connection, the encapsulant is formed over the package units and the connecting bars to encapsulate the chips. The connecting bars are removed prior to the post mold-curing step. Therefore the encapsulant can be cured without deformation or warpage, thereby facilitating the sequent processes.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 7, 2006
    Inventors: Yong-Gill Lee, Jin-Young Hong, Hyung-Jun Park, Jin-Hee Won
  • Patent number: 7087462
    Abstract: The present invention includes providing a leadframe including a metal layer formed on an upper surface of the leadframe and a plurality of units in an array arrangement, in which each unit includes a die pad, a plurality of leads, and a plurality of outer dambars, adhering a die to the die pad, forming a plurality of conductive wires to electrically connect bond pads of the die with bond regions of the leads, forming an encapsulation covering the leadframe, forming a patterned photoresist layer on a lower surface of the leadframe to expose a plurality of interval regions and the outer dambars, performing an etching process to expose the metal layer located in the interval regions and the outer dambars, cutting off the metal layer located in the interval regions by a half cutting process, and performing a singulation process to singulate the units.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: August 8, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sang-Bae Park, Yong-Gill Lee, Hyung-Jun Park, Chang-Young Sohn
  • Patent number: 6984878
    Abstract: A leadless leadframe with an improved die pad for mold locking includes a die pad and a plurality of leads. The leads are arranged around the die pad. A plurality of indentations, such as side semi-vias, are formed on the sidewall of the die pad for filling a package body of the semiconductor package so as to enhance the horizontal mold locking capability of the die pad.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: January 10, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sang-Bae Park, Yong-Gill Lee, Hyung-Jun Park, Kyung-Soo Rho, Jin-Hee Won
  • Publication number: 20050287709
    Abstract: A process for manufacturing a plurality of leadless semiconductor packages includes an electrically testing step to test encapsulated chips in a matrix of a leadless leadframe. Firstly, a leadless leadframe having at least a packaging matrix is provided. The packaging matrix defines a plurality of units and a plurality of cutting streets between the units. The leadless leadframe has a plurality of leads in the units and a plurality of connecting bars connecting the leads along the cutting streets. A plated metal layer is formed on the upper surfaces of the leads and the upper surfaces of the connecting bars. After die-attaching, wire-bonding connection, and encapsulation, the leadless leadframe is etched to remove the connecting bars, then two sawing steps are performed. During the first sawing step, the plated metal layer on the upper surface of the connecting bars is cut out to electrically isolate the leads.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 29, 2005
    Inventors: Yong-Gill Lee, Hyung-Jun Park, Sang-Bae Park
  • Publication number: 20050260795
    Abstract: A method for fabricating leadless packages with mold locking characteristics is disclosed. A provided leadless leadframe has a plurality of units in a matrix, each unit includes an improved die pad with a plurality of indentations, such as semi-vias in the sidewall thereof and a plurality of leads around the die pad. After chip attachment and electrical connection, a plurality of package bodies for semiconductor packages are individually formed on the corresponding units and covered the indentations in order to enhance the horizontal mold locking capability of the die pad. Using punching, connecting bars of the leadless leadframe are removed to isolate the leadless packages.
    Type: Application
    Filed: October 27, 2004
    Publication date: November 24, 2005
    Inventors: Sang-Bae Park, Yong-Gill Lee, Hyung-Jun Park, Kyung-Soo Rho, Jin-Hee Won
  • Publication number: 20050258521
    Abstract: A leadless leadframe with an improved die pad for mold locking includes a die pad and a plurality of leads. The leads are arranged around the die pad. A plurality of indentations, such as side semi-vias, are formed on the sidewall of the die pad for filling a package body of the semiconductor package so as to enhance the horizontal mold locking capability of the die pad.
    Type: Application
    Filed: May 24, 2004
    Publication date: November 24, 2005
    Inventors: Sang-Bae Park, Yong-Gill Lee, Hyung-Jun Park, Kyung-Soo Rho, Jin-Hee Won