Patents by Inventor Yong-Min Yoo

Yong-Min Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240158942
    Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 16, 2024
    Inventors: Yong Min Yoo, Seung Woo Choi, Dong Seok Kang, Jong Won Shon
  • Patent number: 11965262
    Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 23, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Yong Min Yoo, Jong Won Shon, Seung Woo Choi, Dong Seok Kang
  • Publication number: 20240079721
    Abstract: A battery module includes at least two cell assemblies, a module housing having an upper cover formed by a top portion and a first side portion extending downward from a first side edge of the top portion, a first gas passage formed between the first side portion of the upper cover and a first side of the at least two cell assemblies for circulation of gas generated from the at least two cell assemblies, and a flame retardant plate in the first gas passage and extending between the at least two cell assemblies and the module housing, wherein the first side portion of the upper cover is coupled to the flame retardant plate.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Eun-Gyu SHIN, Jeong-O MUN, Jae-Min YOO, Yoon-Koo LEE, Yong-Seok CHOI, Jee-Soon CHOI
  • Publication number: 20240069689
    Abstract: A method of supporting divided screen areas and a mobile terminal employing the same are disclosed. The method includes: generating input signals for one of sequentially and simultaneously activating a plurality of user functions; activating the user functions according to generated input signals; dividing a screen into divided screen areas that correspond to activated user functions; and outputting functional view areas associated with the activated user functions to the corresponding divided screen areas.
    Type: Application
    Filed: September 20, 2023
    Publication date: February 29, 2024
    Inventors: Hyung Min YOOK, Sung Sik YOO, Kang Won LEE, Myeong Lo LEE, Young Ae KANG, Hui Chul YANG, Yong Ki MIN
  • Publication number: 20220145452
    Abstract: Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Inventors: Tae Ho Yoon, Hyung Sang Park, Yong Min Yoo
  • Patent number: 11261523
    Abstract: Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: March 1, 2022
    Assignee: ASM KOREA LTD.
    Inventors: Tae Ho Yoon, Hyung Sang Park, Yong Min Yoo
  • Patent number: 11195845
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: December 7, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Publication number: 20210054519
    Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Yong Min Yoo, Jong Won Shon, Seung Woo Choi, Dong Seok Kang
  • Publication number: 20210035988
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 10876218
    Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 29, 2020
    Assignee: ASM IP HOLDING B.V.
    Inventors: Yong Min Yoo, Jong Won Shon, Seung Woo Choi, Dong Seok Kang
  • Publication number: 20200385859
    Abstract: Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.
    Type: Application
    Filed: March 18, 2020
    Publication date: December 10, 2020
    Inventors: Tae Ho Yoon, Hyung Sang Park, Yong Min Yoo
  • Patent number: 10847529
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in the process of selectively depositing a landing pad in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 24, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 10644025
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10622375
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10504901
    Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 10, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 10438965
    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 8, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Young Jae Kim, Seung Woo Choi, Yong Min Yoo
  • Patent number: 10395921
    Abstract: Provided is a method of forming a thin film having a target thickness T on a substrate by an atomic layer deposition (ALD) method. The method includes n processing conditions each having a film growth rate that is different from the others, and determining a1 to an that are cycles of a first processing condition to an n-th processing condition so that a value of |T?(a1×G1+a2×G2+ . . . +an×Gn)| is less than a minimum value among G1, G2, . . . , and Gn, where n is 2 or greater integer, G1, . . . , and Gn respectively denote a first film growth rate that is a film growth rate of the first processing condition, . . . and an n-th film growth rate that is a film growth rate of the n-th processing condition, and the film growth rate denotes a thickness of a film formed per a unit cycle in each of the processing conditions. The film forming method may precisely and uniformly control a thickness of the thin film when an ALD is performed.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 27, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Dae Youn Kim, Seung Woo Choi, Hyung Wook Noh, Yong Min Yoo, Hak Joo Lee
  • Patent number: 10381226
    Abstract: A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: August 13, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim
  • Patent number: 10249577
    Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 2, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Choong Man Lee, Yong Min Yoo, Young Jae Kim, Seung Ju Chun, Sun Ja Kim
  • Publication number: 20190081072
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo