Patents by Inventor Yongna LI
Yongna LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240196630Abstract: A 3D memory device includes a complementary metal-oxide-semiconductor (CMOS) structure having a page buffer region and a string driver region respectively corresponding to a cell region and a string region in an array structure, wherein the CMOS structure further includes a plurality of page buffers in a folded structure formed in the page buffer region; and string driver circuits formed in the string region.Type: ApplicationFiled: December 28, 2022Publication date: June 13, 2024Inventors: Liang CHEN, Wei LIU, YONGNA LI, Huaguo SHENG
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Patent number: 11991880Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.Type: GrantFiled: September 9, 2020Date of Patent: May 21, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
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Publication number: 20230070357Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: ApplicationFiled: August 15, 2022Publication date: March 9, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Lidong SONG, Yongna LI, Feng PAN, Xiaowang DAI, Dan LIU, Steve Weiyi YANG, Simon Shi-Ning YANG
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Patent number: 10998079Abstract: Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.Type: GrantFiled: May 5, 2020Date of Patent: May 4, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jong Jun Kim, Feng Pan, Jong Seuk Lee, Zhenyu Lu, Yongna Li, Lidong Song, Youn Cheul Kim, Steve Weiyi Yang, Simon Shi-Ning Yang
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Patent number: 10930663Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.Type: GrantFiled: July 26, 2018Date of Patent: February 23, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
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Publication number: 20210043643Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
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Publication number: 20200411547Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.Type: ApplicationFiled: September 9, 2020Publication date: December 31, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Yu Ru HUANG, Qian TAO, Yushi HU, Jun CHEN, Xiaowang DAI, Jifeng ZHU, Yongna LI, Lidong SONG
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Patent number: 10847531Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.Type: GrantFiled: July 26, 2018Date of Patent: November 24, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
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Patent number: 10804287Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.Type: GrantFiled: September 10, 2018Date of Patent: October 13, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
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Publication number: 20200265913Abstract: Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Inventors: Jong Jun KIM, Feng PAN, Jong Seuk LEE, Zhenyu LU, Yongna LI, Lidong SONG, Youn Cheul KIM, Steve Weiyi YANG, Simon Shi-Ning YANG
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Publication number: 20200203285Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: ApplicationFiled: December 31, 2019Publication date: June 25, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Lidong SONG, Yongna LI, Feng PAN, Xiaowang DAI, Dan LIU, Steve Weiyi YANG, Simon Shi-Ning YANG
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Patent number: 10679721Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.Type: GrantFiled: July 26, 2018Date of Patent: June 9, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jong Jun Kim, Feng Pan, Jong Seuk Lee, Zhenyu Lu, Yongna Li, Lidong Song, Youn Cheul Kim, Steve Weiyi Yang, Simon Shi-Ning Yang
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Patent number: 10593624Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.Type: GrantFiled: July 25, 2018Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Deepak Thimmegowda, Aaron Yip, Mark Helm, Yongna Li
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Patent number: 10522474Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: GrantFiled: July 26, 2018Date of Patent: December 31, 2019Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Xiaowang Dai, Dan Liu, Steve Weiyi Yang, Simon Shi-Ning Yang
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Publication number: 20190074291Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.Type: ApplicationFiled: September 10, 2018Publication date: March 7, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
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Publication number: 20190067314Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.Type: ApplicationFiled: July 26, 2018Publication date: February 28, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
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Publication number: 20190057756Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.Type: ApplicationFiled: July 26, 2018Publication date: February 21, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jong Jun Kim, Feng Pan, Jong Seuk Lee, Zhenyu Lu, Yongna Li, Lidong Song, Youn Cheul Kim, Steve Weiyi Yang, Simon Shi-Ning Yang
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Publication number: 20190051610Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: ApplicationFiled: July 26, 2018Publication date: February 14, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Lidong SONG, Yongna LI, Feng PAN, Xiaowang DAI, Dan LIU, Steve Weiyi YANG, Simon Shi-Ning YANG
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Publication number: 20180331034Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.Type: ApplicationFiled: July 25, 2018Publication date: November 15, 2018Inventors: Deepak THIMMEGOWDA, Aaron YIP, Mark HELM, Yongna LI
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Patent number: 10043751Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.Type: GrantFiled: March 30, 2016Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Deepak Thimmegowda, Aaron Yip, Mark Helm, Yongna Li