Abstract: In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.

Abstract: A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature compensation circuit configured to receive the sense voltage and produce a temperature compensation control signal to control a compensation capacitor array of an oscillator. The temperature compensation circuit may be configured to calibrate the control signal to have a first value at a first temperature. The temperature compensation circuit may also be configured to calibrate a trimming level (e.g., slope) of the control signal.

Abstract: Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.

Abstract: In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

Abstract: In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.

Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.

Abstract: A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature compensation circuit configured to receive the sense voltage and produce a temperature compensation control signal to control a compensation capacitor array of an oscillator. The temperature compensation circuit may be configured to calibrate the control signal to have a first value at a first temperature. The temperature compensation circuit may also be configured to calibrate a trimming level (e.g., slope) of the control signal.

Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Abstract: A divider is disclosed that presents an enhanced duty cycle for use with precision oscillators in clock sources. In one example, the invention includes a first divider chain to receive an input clock and produce a first divided output, a second divider chain to receive the input clock and produce a second divided output, and a combiner to combine the first and second divided output to produce a third divided output with a duty cycle greater than the first and second divided output.

Abstract: A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators.

Abstract: A charge pump that generates a bias input to affect an output voltage of the charge pump is described herein. The charge pump may include a charge pump stage, a replica charge pump stage, and a self-biased differential amplifier. In some instances, the charge pump may be incorporated into a delay locked loop or a phase locked loop.

Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators.

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract: A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The charge pump generates an operational bias voltage during operation of the first circuit to control a delay of the delay cells. A fast lock circuit is coupled to an output of the charge pump to precharge the output of the charge pump with a startup bias voltage prior to enabling the charge pump.