Abstract: A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point.

Abstract: A shift register unit and a method of driving the shift register unit, a gate driving circuit, and a display device. The shift register unit includes: a first shift register configured to generate a first control output signal (CR1) and a second control output signal (CR2) based on a signal at a first clock signal terminal (CLKD); and a second shift register configured to generate a second output signal (OUT2) based on a signal at a third clock signal terminal (CLKE2), wherein a first pull-down node (PD1_1) of the first shift register is connected to a second pull-down node (PD2_2) of the second shift register, and a second pull-down node (PD1_2) of the first shift register is connected to a first pull-down node (PD2_1) of the second shift register.

Abstract: A shift register unit includes a first input/output unit which includes a first pull-down control circuit and a first auxiliary input circuit, and a second input/output unit which includes a second pull-down control circuit and a second auxiliary input circuit. The first pull-down control circuit controls a level of a first pull-down node. The first auxiliary input circuit is coupled to the first pull-down control circuit and controls the first pull-down control circuit together with a level of a first pull-up node in response to a display control signal and a blanking control signal. The second pull-down control circuit controls a level of a second pull-down node. The second auxiliary input circuit is coupled to the second pull-to down control circuit and controls the second pull-down control circuit together with a level of a second pull-up node in response to the display control signal and the blanking control signal.

Abstract: The present disclose is related to an array substrate. The array substrate may include a base substrate; a driving transistor on the base substrate; an insulating layer on the driving transistor, the insulating layer comprising a via hole above a first electrode of the driving transistor; a conductive portion on the insulating layer; and a light emitting device on the conductive portion and electrically connected to the conductive portion. The conductive portion may be electrically connected to the first electrode of the driving transistor through the via hole. The light emitting device may be above the via hole, and an orthographic projection of the light emitting device on the base substrate may cover an orthographic projection of the via hole on the base substrate.

Abstract: A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.

Abstract: Provided are a pixel structure, a method for driving the same and a display substrate. The pixel structure includes N pixel circuits and a power writing control circuit, N?2 and N is an integer. Each pixel circuit includes a pixel driving sub-circuit and a light-emitting device. The power writing control circuit provides, according to a voltage regulation control signal, a first power voltage for each pixel circuit in a light-emitting phase. The pixel driving sub-circuit provides, according to a data voltage signal, a driving current for the light-emitting device under the control of a first scanning signal. Light-emitting devices in the pixel circuits are sequentially connected in series, a first electrode of the light-emitting device in the first pixel circuit is connected to the power writing control circuit, a second electrode of the light-emitting device in the Nth pixel circuit is connected to a second power terminal.

Abstract: A driving backplane includes a base substrate, and data lines, a first gate line, a second gate line and pixel driving circuits that are disposed on the base substrate. The first gate line and the second gate line are adjacent. Each pixel driving circuit includes a first transistor including an active layer. The active layer includes an active portion, a first conductive portion and a second conductive portion. Active portions of first transistors further include first contact portions. The pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit that are coupled to a data line and the first gate line. A first conductive portion in the first pixel driving circuit and a first conductive portion in the second pixel driving circuit are in contact through a first contact portion, and are coupled to the data line through the first contact portion.

Abstract: A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.

Abstract: A display panel has a display area including a plurality of pixel areas arranged in an array and a plurality of gate driving circuit areas. Each pixel area includes a pixel light-emitting sub-area and a pixel circuit sub-area arranged in a first direction. Pixel areas in each row correspond to at least two gate driving circuit areas each located between two adjacent pixel areas in this row. The display panel includes a gate driving circuit and a plurality of light-shielding portions. The gate driving circuit includes a plurality of shift registers that are cascaded. Each shift register includes a plurality of transistor groups, and each transistor group includes at least one transistor. Each light-shielding portion is located in a gate driving circuit area in which a transistor group is disposed, and is disposed on a periphery of the transistor group, and is electrically connected to a power supply signal line.

Abstract: A shift register includes a first scan unit including a first input circuit and a first output circuit, and a second scan unit including a second input circuit, a second output circuit, and a potential boost circuit. The first input circuit is configured to transmit an input signal to a first pull-up node. The first output circuit is configured to, under a control of a voltage of the first pull-up node, output a shift signal and a first scan signal. The second input circuit is configured to transmit the input signal to a second pull-up node. The second output circuit is configured to output a second scan signal under a control of a voltage of the second pull-up node. The potential boost circuit is configured to boost the voltage of the second pull-up node in cooperation with the second output circuit.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.

Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit and a control sub-circuit. The input sub-circuit is coupled to a first input signal terminal and a pull-up node, and configured to, under control of a first input signal, transmit the first input signal to the pull-up node. The output sub-circuit is at least coupled to the pull-up node, a first clock signal terminal and a first signal output terminal, and configured to transmit a first clock signal to the first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is coupled to at least one first reference node, at least one first control signal terminal and the pull-up node, and configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A multiplexer circuit includes a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit configured to transmit an input signal received at a input signal terminal to a first output terminal in response to a first control signal received at a first control terminal, and transmit a voltage of a power supply voltage terminal to the first output terminal in response to a second control signal received at a second control terminal. The second selection sub-circuit configured to transmit the input signal received at the input signal terminal to a second output terminal in response to a third control signal received at a third control terminal, and transmit the voltage of the power supply voltage terminal to the second output terminal in response to a fourth control signal received at a fourth control terminal.

Abstract: Disclosed is a shift register unit set, a gate driving circuit and a display apparatus, the shift register set including: cascaded n shift register units, and an ith stage of shift register unit in the shift register unit set includes: a first input sub-circuit and a second input sub-circuit, wherein the first input sub-circuit includes: a charging sub-circuit, a storing sub-circuit, an isolating sub-circuit, an output sub-circuit, a first electric leakage prevention sub-circuit configured to input an operation potential to the isolating sub-circuit under the control of the blanking pull-up control node, and a second electric leakage prevention sub-circuit configured to input the operation potential to a second electrode of the isolating transistor under the control of the first pull-up node, wherein there is an overlap among n composite output signals output by the n shift register units, n and i are positive integers, and 1?i?n.

Abstract: The present application discloses a shift-register unit circuit including a first input sub-circuit configured to receive a display-input signal from a display-input terminal and input a display output-control signal to a first node based on the display-input signal during a display period of one cycle of displaying one frame of image. The shift-register unit circuit also includes a second input sub-circuit configured to receive a blank-input signal for charging a blank-control node, and configured to input a blank-output-control signal to the first node based on the blank-input signal during a blank period of the one cycle. The shift-register unit circuit further includes an output sub-circuit configured to output a hybrid signal controlled by the first node. The second input sub-circuit is also configured, before an end of the blank period, to receive a first blank-reset signal to reset the blank-control node.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a banking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, wherein the composite output signal includes a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: An integrated drying process and device for dry granulated slag and sludge. The process comprises the following steps: 1) slag ball mixing and soaking: high-temperature slag and steel balls are fully mixed and exchange heat therebetween, the high-temperature slag is cooled because the heat thereof is quickly absorbed by the steel balls and is crushed to form granular slag, and the temperature of the steel balls rises because the steel balls absorb the heat of the high-temperature slag; and 2) sludge drying: the high-temperature steel balls are conveyed to a sludge drying device to be mixed with injected sludge, the sludge is dried, the steel balls are separated from the sludge when the water content of the sludge reaches a set value, and the steel balls and the sludge are separately discharged.

Abstract: A gate driving unit includes an Nth stage of shift register unit and an (N+1)th stage of shift register unit, N is a positive integer. The Nth stage of shift register unit includes an Nth stage of pull-up node control circuit, and the (N+1)th stage of shift register unit includes an (N+1)th stage of pull-up node control circuit. The Nth stage of pull-up node control circuit is electrically connected to an Nth stage of pull-up node and a control line, controls a potential of the Nth stage of pull-up node under the control of a control signal inputted by the control line. The (N+1)th stage of pull-up node control circuit is electrically connected to an (N+1)th stage of pull-up node and the control line, respectively, and controls a potential of the (N+1)th stage of pull-up node under the control of the control signal inputted by the control line.