Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.

Abstract: A computing system including a plurality of processing devices configured to execute a Mixture-of-Experts (MoE) layer. The processing devices are configured to execute the MoE layer at least in part by receiving an input tensor including input tokens. Executing the MoE layer further includes computing a gating function output vector based on the input tensor and computing a sparse encoding of the input tensor and the gating function output vector. The sparse encoding indicates one or more destination expert sub-models. Executing the MoE layer further includes dispatching the input tensor for processing at the one or more destination expert sub-models, and further includes computing an expert output tensor. Executing the MoE layer further includes computing an MoE layer output at least in part by computing a sparse decoding of the expert output tensor. Executing the MoE layer further includes conveying the MoE layer output to an additional computing process.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AH traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.

Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AR traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.

Abstract: The present concepts relate to identifying entities based on their behavior using machine learning models. Where an entity may be a bot or a human, the entity's requests sent to a website are used to generate a graph. The graph may be used to create an image, such that the image reflects the entity's browsing behavior. A machine learning model, which has been trained using a first training set of images that correspond to bots and a second training set of images that correspond to humans, can determine whether the entity is a bot or a human by performing an image classification.

Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.

Abstract: In accordance with implementations of the subject matter described herein, there is provided a solution for streaming communication between devices. In this solution, a memory of a first device comprising a ring buffer is allocated to be dedicated for storing a data stream of an application to be transmitted to a second electronic device. The application of the first device writes data to be transmitted into the ring buffer, to form a portion of the first data stream, and a write pointer of the ring buffer is thus updated. A portion of data is read based on a source memory address from the ring buffer via the interface device. The interface device also transmits the data portion to a second device. The read data portion is stored in a dedicated ring buffer of the memory. In accordance with the solution, an efficient streaming communication interface is provided between devices.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.

Abstract: The present concepts relate to identifying entities based on their behavior using machine learning models. Where an entity may be a bot or a human, the entity's requests sent to a website are used to generate a graph. The graph may be used to create an image, such that the image reflects the entity's browsing behavior. A machine learning model, which has been trained using a first training set of images that correspond to bots and a second training set of images that correspond to humans, can determine whether the entity is a bot or a human by performing an image classification.

Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AH traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.

Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.

Abstract: This application describes routing packets from a source server to a plurality of ports of a switch. The switch is programmed by the control server and is used to direct incoming data packets to one or more ports of the switch in a manner that reduces congestion of incoming data packets to a destination server. Further, the control server queries congestion information from the switch, and then sends congestion notification back to the source server to either increase or decrease the amount of data being sent to the destination server.

Abstract: A system, method or computer readable medium to provide efficient congestion notification is described herein. In various embodiments, a packet is received at an intermediate node of one or more data center networks. A current queue length at the intermediate node is determined. A threshold value for the current queue length is tuned by dynamically computing an upper bound and a lower bound based at least in part on the network. The packet is marked to indicate possible congestion in the one or more data center networks when the current queue length exceeds the threshold value. In some embodiments, the packet is marked when it is being de-queued. In a further embodiment, Flexible Initial Packet Size (FIPS) may be utilized to improve the efficiency of the tuning.