Abstract: An adaptive continuous-time linear equalizer (CTLE) includes a CTLE cell including input terminals and output terminals, a low-pass filter configured to respectively output low-band differential signals obtained by respectively low-pass filtering differential output signals, and an error amplifier configured to amplify a difference between the low-band differential signals and output the difference as a control voltage. The CTLE cell includes first and second transistors each including an input terminal and an output terminal and an offset compensator configured to adjust a potential difference between a supply voltage source and the output terminal according to the control voltage.

Abstract: A method of adaptively training an equalizer system of a PAM-N receiver is disclosed. The method of training an equalizer system according to the present invention employs a training pattern including a first training data pattern and second training data pattern to tune the continuous-time linear equalizer, decision feedback equalizer and sampler constituting the equalizer system before use in actual communication enabling long-distance, high-speed communication.

Abstract: A method of adaptively training an equalizer system of a PAM-N receiver is disclosed. The method of training an equalizer system according to the present invention employs a training pattern including a first training data pattern and second training data pattern to tune the continuous-time linear equalizer, decision feedback equalizer and sampler constituting the equalizer system before use in actual communication enabling long-distance, high-speed communication.

Abstract: A PAM-N receiver capable of adaptively adjusting threshold voltages determining a level of a received signal and a method of adaptively adjusting threshold voltages thereof are disclosed. According to the method of the present invention, the result of comparison between reference data levels and the level of data in the received signal are used to adjust the reference data levels, and the threshold voltages of a PAM-N receiver are adaptively calculated from the adjusted reference data levels, thereby reflecting transmission line conditions and Inter-Symbol Interference.

Abstract: A PAM-N receiver capable of adaptively adjusting threshold voltages determining a level of a received signal and a method of adaptively adjusting threshold voltages thereof are disclosed. According to the method of the present invention, the result of comparison between reference data levels and the level of data in the received signal are used to adjust the reference data levels, and the threshold voltages of a PAM-N receiver are adaptively calculated from the adjusted reference data levels, thereby reflecting transmission line conditions and Inter-Symbol Interference.

Abstract: A PAM4 receiver including an adaptive continuous-time linear equalizer and a method for training the same are disclosed. The PAM4 receiver and the method for training the same of the present invention employs a training pattern including a first training data pattern and second training data pattern to adaptively tune the PAM4 receiver to achieve accurate data reception and long-distance, high-speed communication.

Abstract: A PAM4 receiver including an adaptive continuous-time linear equalizer and a method for training the same are disclosed. The PAM4 receiver and the method for training the same of the present invention employs a training pattern including a first training data pattern and second training data pattern to adaptively tune the PAM4 receiver to achieve accurate data reception and long-distance, high-speed communication.

Abstract: A DFE circuit for use in a semiconductor memory device and an initializing method thereof. In the method of initializing a DFE circuit used in a semiconductor memory device having a discontinuous data transmission, the DFE circuit may be used for changing a sampling reference level in response to a level of previous data and sampling transmission data. The method includes terminating a data channel having a transmission of the transmission data at a predefined termination level, and controlling a sampling start time point of the transmission data as a time point preceding a transmission time point of the transmission data by a predefined time. Further, an initialization may be performed of the previous data on the basis of initialization data obtained through a pre-sampling of the data channel at a sampling start time point of the transmission data, thereby obtaining an initialization of the DFE circuit and compensating for a feedback delay.

Abstract: A DFE circuit for use in a semiconductor memory device and an initializing method thereof. In the method of initializing a DFE circuit used in a semiconductor memory device having a discontinuous data transmission, the DFE circuit may be used for changing a sampling reference level in response to a level of previous data and sampling transmission data. The method includes terminating a data channel having a transmission of the transmission data at a predefined termination level, and controlling a sampling start time point of the transmission data as a time point preceding a transmission time point of the transmission data by a predefined time. Further, an initialization may be performed of the previous data on the basis of initialization data obtained through a pre-sampling of the data channel at a sampling start time point of the transmission data, thereby obtaining an initialization of the DFE circuit and compensating for a feedback delay.

Abstract: A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-?m CMOS technology, and shows 10?12 bit error rate up to speeds of 3 Gbps.

Abstract: A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signal is used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

Abstract: A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

Abstract: A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

Abstract: A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

Abstract: For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3× oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and inter-symbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25 &mgr;m CMOS technology, operates at 2.5 GBaud over a 10-m 150-&OHgr; STP cable and at 1.

Abstract: A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

Abstract: A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

Abstract: A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signalis used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

Abstract: A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

Abstract: A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop and a phase acquisition loop. The frequency acquisition loop delays the reference clock to produce an intermediate clock which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock to produce a local clock synchronized to the reference clock.