Abstract: A depth-wise convolution acceleration device using an MAC array processor structure according to the present invention may include a data output unit, which receives a data of each row of the image from the data buffer and inputs the data into convolution operation blocks while shifting the data N?1 times according to the kernel size (N×N) and a weight output unit, which receives the kernel data from the kernel buffer and sequentially inputs a weight value constituting the kernel data to each of the row convolution operation blocks, and inputs the weight delaying by N clocks if the row increases as N rows.

Abstract: An electronic device is provided. The electronic device includes a housing, a display configured to be exposed through one surface of the housing, a communication module configured to communicate over a first network compliant with a first protocol or a second network compliant with a second protocol, a processor configured to be electrically connected with the display and the communication module, and a memory configured to be electrically connected with the processor and store a specified application. The memory stores instructions, that when executed, cause the processor 420 to execute the specified application, designate a CP server by interacting with a platform server over the second network, receive an initial response message generated by the designated CP server over the first network, and verify a first identifier of the designated CP server based on the first protocol from a source of the initial response message.

Abstract: An electronic device is provided. The electronic device includes a housing, a display configured to be exposed through one surface of the housing, a communication module configured to communicate over a first network compliant with a first protocol or a second network compliant with a second protocol, a processor configured to be electrically connected with the display and the communication module, and a memory configured to be electrically connected with the processor and store a specified application. The memory stores instructions, that when executed, cause the processor 420 to execute the specified application, designate a CP server by interacting with a platform server over the second network, receive an initial response message generated by the designated CP server over the first network, and verify a first identifier of the designated CP server based on the first protocol from a source of the initial response message.

Abstract: A power device package according to the one embodiment of the present invention includes an insulating substrate with an interconnection pattern disposed on the insulating substrate. The interconnection pattern comprises a single conductive layer comprising a first metal layer, and a multiple conductive layer comprising another first metal layer and a second metal layer disposed on the another first metal layer. A plurality of wires are attached to an upper surface of the single conductive layer and/or an upper surface of the second metal layer of the multiple conductive layer. Contact pads on a power control semiconductor chip and a low power semiconductor chip driving the power control semiconductor chip are electrically connected to the wires.

Abstract: A method is disclosed. The method includes forming a substrate with a leadframe and a molding compound. The molding compound fills internal spaces in the leadframe and forms a dam structure. An optical emitter and an optical receiver are placed on the substrate. An optically transmissive medium is formed between the optical emitter and optical receiver.

Abstract: A method is disclosed. The method includes forming a substrate with a leadframe and a molding compound. The molding compound fills internal spaces in the leadframe and forms a dam structure. An optical emitter and an optical receiver are placed on the substrate. An optically transmissive medium is formed between the optical emitter and optical receiver.

Abstract: A power device package according to the one embodiment of the present invention includes an insulating substrate with an interconnection pattern disposed on the insulating substrate. The interconnection pattern comprises a single conductive layer comprising a first metal layer, and a multiple conductive layer comprising another first metal layer and a second metal layer disposed on the another first metal layer. A plurality of wires are attached to an upper surface of the single conductive layer and/or an upper surface of the second metal layer of the multiple conductive layer. Contact pads on a power control semiconductor chip and a low power semiconductor chip driving the power control semiconductor chip are electrically connected to the wires.

Abstract: A semiconductor package having an oxidation free copper wire that connects a semiconductor chip and a pad is provided. The copper wire is coated with an oxidation free layer. The copper wire provides good electrical characteristics and reliability.