Patents by Inventor Yongxi Zhang
Yongxi Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9553011Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.Type: GrantFiled: December 10, 2013Date of Patent: January 24, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Eugen Mindricelu, Sameer Pendharkar, Seetharaman Sridhar
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Patent number: 9543299Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.Type: GrantFiled: September 22, 2015Date of Patent: January 10, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar, Henry Litzmann Edwards
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Patent number: 9525060Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.Type: GrantFiled: December 8, 2014Date of Patent: December 20, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer Pendharkar, Seetharaman Sridhar
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Publication number: 20160336427Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Yongxi ZHANG, Sameer P. PENDHARKAR, Scott G. BALSTER
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Publication number: 20160254346Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.Type: ApplicationFiled: February 28, 2015Publication date: September 1, 2016Applicant: Texas Instruments IncorporatedInventors: Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P. Pendharkar
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Patent number: 9431480Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.Type: GrantFiled: March 27, 2015Date of Patent: August 30, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar, Scott G. Balster
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Publication number: 20160093612Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.Type: ApplicationFiled: December 10, 2015Publication date: March 31, 2016Inventors: Yongxi Zhang, Sameer P. Pendharkar
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Patent number: 9245998Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.Type: GrantFiled: December 22, 2014Date of Patent: January 26, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar
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Publication number: 20150340496Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: Texas Instruments IncorporatedInventors: YONGXI ZHANG, PHILIP L. HOWER, SAMEER P. PENDHARKAR, JOHN LIN, GURU MATHUR, SCOTT BALSTER, VICTOR SINOW
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Publication number: 20150187934Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.Type: ApplicationFiled: December 22, 2014Publication date: July 2, 2015Inventors: Yongxi Zhang, Sameer P. Pendharkar
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Publication number: 20150171211Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.Type: ApplicationFiled: December 8, 2014Publication date: June 18, 2015Inventors: Yongxi ZHANG, Sameer PENDHARKAR, Seetharaman SRIDHAR
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Publication number: 20150118861Abstract: A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (?) 1017 atoms/cm3 with a boron doping or n-type doping concentration of between 1×1012 cm?3 and 5×1014 cm?3. Before any oxidization processing, the LDCBS substrate is annealed at a nucleating temperature between 550° C. and 760° C. for a nucleating time that nucleates the oxygen atoms in a sub-surface region of the LDCBS substrate to form oxygen precipitates therefrom. After the annealing, a surface of the LDCBS substrate or an epitaxial layer on the surface of the LDCBS substrate is initially oxidized in an oxidizing ambient at a peak temperature of between 800° C. and 925° C. for a time less than or equal (?) to 30 minutes.Type: ApplicationFiled: October 22, 2014Publication date: April 30, 2015Inventors: BRADLEY DAVID SUCHER, RICK L. WISE, SCOTT GERARD BALSTER, SEUNG-SA PARK, PHILIP LELAND HOWER, JOHN LIN, GURU MATHUR, YONGXI ZHANG
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Publication number: 20140183662Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.Type: ApplicationFiled: December 10, 2013Publication date: July 3, 2014Inventors: Yongxi ZHANG, Eugen MINDRICELU, Sameer PENDHARKAR, Seetharaman SRIDHAR
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Patent number: 8749024Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.Type: GrantFiled: November 6, 2013Date of Patent: June 10, 2014Assignee: Texas Instruments IncorporatedInventors: Sameer Pendharkar, Marie Denison, Yongxi Zhang
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Publication number: 20140061859Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.Type: ApplicationFiled: November 6, 2013Publication date: March 6, 2014Applicant: Texas Instruments IncorporatedInventors: Sameer Pendharkar, Marie Denison, Yongxi Zhang
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Patent number: 8598008Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.Type: GrantFiled: October 20, 2011Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, Marie Denison, Yongxi Zhang
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Publication number: 20120098098Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.Type: ApplicationFiled: October 20, 2011Publication date: April 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P. Pendharkar, Marie Denison, Yongxi Zhang