Abstract: A VCSEL array comprises a plurality of non-isolated VCSEL emitters. Each non-isolated VCSEL emitter comprises a first reflector region, a current confining oxide layer, an oxide aperture, an active region, and a second reflector region. The current confining oxide layer and oxide aperture are made by oxidizing a relatively high Al-content layer via separate oxidation holes. The separate oxidation holes surround the oxide aperture. The first reflector regions of the plurality of non-isolated VCSEL structures are connected such that they are not isolated from each other completely by any isolation structure, and the second reflector regions of the plurality of non-isolated VCSEL structures are connected such that they are not isolated from each other completely by any isolation structure.

Abstract: A bottom-emitting multijunction VCSEL array includes a first reflector region, a multijunction active region, and a second reflector region. In one aspect, the multijunction VCSEL array is attached to a submount by flip-chip bonding. In another aspect, the multijunction VCSEL array further includes a contact layer formed between the first reflector region and the substrate. The multijunction VCSEL array is attached to a submount by flip-chip bonding.

Abstract: A VCSEL array comprises series-connected VCSEL sub-arrays formed on a single chip. The VCSEL sub-arrays each comprises VCSEL emitters fabricated on a semi-insulating layer. A common cathode contact of a VCSEL sub-array is electrically connected to a common anode contact of a neighboring VCSEL sub-array. To reduce leakage, the bandgap energy level of the semi-insulating layer is higher than the photon energy of the output beam. In one embodiment, the semi-insulating layer is grown on a conductive layer. A common cathode contact of the last VCSEL sub-array in a series is electrically connected to the conductive layer. In another embodiment, multiple wire-bonding areas are electrically connected to common anode contacts of multiple VCSEL sub-arrays respectively. The wire-bonding areas provide different input impedance options for a VCSEL array.

Abstract: A VCSEL array and the method of manufacturing the array are disclosed. The VCSEL array comprises a substrate and a plurality of VCSEL structures formed on the substrate in a regular pattern. A customized metal layer is deposited to electrically connect a selected number but not all of the plurality of VCSEL structures. The selected number of VCSEL structures form an array of a predetermined irregular pattern.

Abstract: The present invention discloses a VCSEL array that can function in at least two different operational modes. In one operational mode, the VCSEL array functions as a regular-patterned array; and in the other operational mode, the VCSEL array functions as an irregular-patterned array. Thus, the same VCSEL chip may be used as an illumination light source or a structural light method light source for 3D sensing, depending on the selected operational mode.

Abstract: The present invention discloses a VCSEL array that is divided into at least a first and a second area. The first area covers the center of the array and is surrounded by the second area. The first area would experience higher temperature than the second area after the VCSELs in both areas are turned on for a given time period. VCSELs in the first area are electrically connected to a first metal layer portion. VCSELs in the second area are electrically connected to a second metal layer portion. The first and second metal layer portions are electrically insulated from each other.

Abstract: A P-N junction gate high electron mobility transistor (HEMT) device with a self-aligned gate structure and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a heterojunction comprising a barrier layer formed on a channel layer. A gate layer is formed on the barrier layer, the gate layer comprising a P-type group III-V semiconductor material suitable for depleting the carriers of a current conducting channel at the heterojunction when the HEMT device is off. A gate electrode comprising indium tin oxide (ITO) is formed on the gate layer, the gate electrode and the gate layer having substantially the same length.

Abstract: Disclosed herein is a non-contact package useful when an article to be stored or shipped in the package includes a sensitive surface, the performance of which will be detrimentally affected if the sensitive surface is contacted with a nominal amount of mechanical force. A fluid environment which does not produce sufficient mechanical force to detrimentally affect the sensitive surface may be used in contact with the sensitive surface to prevent an undesirable chemical reaction on the sensitive surface. A fluid environment may also be used inside the package to support surrounding walls of the package so that such walls do not contact the sensitive surface and/or to dissipate force applied to the exterior of the package so that the sensitive surface will not be damaged.

Abstract: A guard for an electrostatic chuck includes a ceramic annulus that has an inner surface shaped to fit around a circumference of the electrostatic chuck, and an outer surface having (i) a top portion with a recessed trench and (ii) a side portion. A metal coating is provided on the top portion of the outer surface.

Abstract: In a method of cleaning and refurbishing a process chamber component having a metal coating having a surface thereon, the surface of the metal coating is immersed in an acidic solution to remove at least a portion of the process deposits from the surface. Thereafter, the surface of the metal coating is immersed in a basic solution to remove substantially all the metal coating. The component may optionally be bead blasting to roughen a surface of the component, and the metal coating may be re-formed.

Abstract: Disclosed herein is a method of roughening a ceramic surface by forming mechanical interlocks in the ceramic surface by a chemical etching process, a thermal etching process, or a laser micromachining process. Also disclosed herein are components for use in semiconductor processing chambers (in particular, a deposition ring for use in a PVD chamber) which have at least one ceramic surface having mechanical interlocks formed therein by chemical etching, thermal etching, or laser micromachining. Ceramic surfaces which have been roughened according to the chemical etching, thermal etching, or laser micromachining process of the invention are less brittle and damaged than ceramic surfaces which are roughened using conventional grit blasting techniques. The method of the invention results in a roughened ceramic surface which provides good adherence to an overlying sacrificial layer (such as aluminum).

Abstract: Disclosed herein is a non-contact package useful when an article to be stored or shipped in the package includes a sensitive surface, the performance of which will be detrimentally affected if the sensitive surface is contacted with a nominal amount of mechanical force. A fluid environment which does not produce sufficient mechanical force to detrimentally affect the sensitive surface may be used in contact with the sensitive surface to prevent an undesirable chemical reaction on the sensitive surface. A fluid environment may also be used inside the package to support surrounding walls of the package so that such walls do not contact the sensitive surface and/or to dissipate force applied to the exterior of the package so that the sensitive surface will not be damaged.

Abstract: A guard for an electrostatic chuck includes a ceramic annulus that has an inner surface shaped to fit around a circumference of the electrostatic chuck, and an outer surface having (i) a top portion with a recessed trench and (ii) a side portion. A metal coating is provided on the top portion of the outer surface.

Abstract: In a method of cleaning and refurbishing a process chamber component having a metal coating having a surface thereon, the surface of the metal coating is immersed in an acidic solution to remove at least a portion of the process deposits from the surface. Thereafter, the surface of the metal coating is immersed in a basic solution to remove substantially all the metal coating. The component may optionally be bead blasting to roughen a surface of the component, and the metal coating may be reformed.

Abstract: A method of fabricating a process chamber component that has a ceramic form with grains and grain boundary regions. In the method, the component is bead blasted to provide a surface having a relatively low roughness average of less than about 150 microinches. The component is dipped into a solution having a concentration that is sufficiently low to reduce etching of grain boundary regions of the ceramic form. A metal coating is formed over at least a portion of the ceramic form. The component fabricated by this method can tolerate thicker deposits of sputtered material in a sputtering process without the sputtered deposit accumulates causing spalling of the coating of the component.

Abstract: A substrate processing chamber has a component having a surface that is exposed inside the chamber. The exposed surface can have a pattern of recesses that are spaced apart from one another, each recess having an opening, sidewalls, and a bottom wall. The recesses are formed by directing a pulsed laser beam onto a position on a surface of the structure for a time sufficiently long to vaporize a portion of the structure at that position. The component can also be a gas distributor having an enclosure with plurality of laser drilled gas outlets having first and second openings with different diameters to reduce an ingress of a plasma into the enclosure. The laser drilled gas outlets can also have rounded edges.

Abstract: A method of fabricating a process chamber component that has a ceramic form with grains and grain boundary regions. In the method, the component is bead blasted to provide a surface having a relatively low roughness average of less than about 150 microinches. The component is dipped into a solution having a concentration that is sufficiently low to reduce etching of grain boundary regions of the ceramic form. A metal coating is formed over at least a portion of the ceramic form. The component fabricated by this method can tolerate thicker deposits of sputtered material in a sputtering process without the sputtered deposit accumulates causing spalling of the coating of the component.

Abstract: Disclosed herein is a method of roughening a ceramic surface by forming mechanical interlocks in the ceramic surface by a chemical etching process, a thermal etching process, or a laser micromachining process. Also disclosed herein are components for use in semiconductor processing chambers (in particular, a deposition ring for use in a PVD chamber) which have at least one ceramic surface having mechanical interlocks formed therein by chemical etching, thermal etching, or laser micromachining. Ceramic surfaces which have been roughened according to the chemical etching, thermal etching, or laser micromachining process of the invention are less brittle and damaged than ceramic surfaces which are roughened using conventional grit blasting techniques. The method of the invention results in a roughened ceramic surface which provides good adherence to an overlying sacrificial layer (such as aluminum).