Patents by Inventor Yongxun Liu
Yongxun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10636751Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.Type: GrantFiled: August 3, 2016Date of Patent: April 28, 2020Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE & TECHNOLOGYInventors: Yohei Hori, Yongxun Liu, Shinichi Ouchi, Tetsuji Yasuda, Meishoku Masahara, Toshifumi Irisawa, Kazuhiko Endo, Hiroyuki Ota, Tatsuro Maeda, Hanpei Koike, Yasuhiro Ogasahara, Toshihiro Katashita, Koichi Fukuda
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Publication number: 20190019766Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.Type: ApplicationFiled: August 3, 2016Publication date: January 17, 2019Inventors: Yohei Hori, Yongxun Liu, Shinichi Ouchi, Tetsuji Yasuda, Meishoku Masahara, Toshifumi Irisawa, Kazuhiko Endo, Hiroyuki Ota, Tatsuro Maeda, Hanpei Koike, Yasuhiro Ogasahara, Toshihiro Katashita, Koichi Fukuda
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Patent number: 8399879Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.Type: GrantFiled: June 5, 2009Date of Patent: March 19, 2013Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi Ouchi, Kunihiro Sakamoto, Meishoku Masahara
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Patent number: 8399330Abstract: A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.Type: GrantFiled: May 22, 2012Date of Patent: March 19, 2013Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi Ouchi, Kunihiro Sakamoto, Meishoku Masahara
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Publication number: 20120238082Abstract: A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.Type: ApplicationFiled: May 22, 2012Publication date: September 20, 2012Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Yongxun LIU, Takashi Matsukawa, Kazuhiko Endo, Shinichi Ouchi, Kunihiro Sakamoto, Meishoku Masahara
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Patent number: 8077510Abstract: An SRAM device including a memory cell, the memory cell having two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation.Type: GrantFiled: December 6, 2007Date of Patent: December 13, 2011Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Shinichi Ouchi, Yongxun Liu, Meishoku Masahara, Takashi Matsukawa, Kazuhiko Endo
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Patent number: 8040717Abstract: A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, and a sixth four-terminal double-gate FET with the first conductivity type. The third and the fourth four-terminal double-gate FETs form select transistors, and the first, second, fifth and sixth four-terminal double-gate FETs form a complementary metal-oxide-semiconductor (CMOS) inverter.Type: GrantFiled: December 20, 2007Date of Patent: October 18, 2011Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Shinichi Ouchi, Yongxun Liu, Meishoku Masahara, Takashi Matsukawa, Kazuhiko Endo
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Patent number: 7999321Abstract: A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap.Type: GrantFiled: May 9, 2008Date of Patent: August 16, 2011Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Yongxun Liu, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo, Shinichi Ouchi
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Publication number: 20110073842Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.Type: ApplicationFiled: June 5, 2009Publication date: March 31, 2011Applicant: National Institue of Advanced Industrial Science and TechnologyInventors: Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi Ouchi, Kunihiro Sakamoto, Meishoku Masahara
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Publication number: 20110057163Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor.Type: ApplicationFiled: June 5, 2009Publication date: March 10, 2011Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi Ouchi, Kunihiro Sakamoto, Meishoku Masahara
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Publication number: 20100315861Abstract: In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a third four-terminal double-gate FETs which are connected in series with each other and have a second conductivity type; a fourth and a fifth four-terminal double-gate FETs which are connected in series with each other and have the second conductivity type; a sixth four-terminal double-gate FET with the first conductivity type, wherein the third and the fourth four-terminal double-gate FETs form select transistors, and the first, the second, the fifth and the sixth four-terminal double-gate FETs form a CMOS inverter, logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on the side facing the second and the third semiconductor thin plates, respectively, while threshold voltage control gaType: ApplicationFiled: December 20, 2007Publication date: December 16, 2010Applicant: NATIONAL INSTITUTE OF ADVANCED IND. SCI & TECHInventors: Shinichi Ouchi, Yongxun Liu, Meishoku Masahara, Takashi Matsukawa, Kazuhiko Endo
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Publication number: 20100213546Abstract: A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap.Type: ApplicationFiled: May 9, 2008Publication date: August 26, 2010Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Yongxun Liu, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo, Shinichi Ouchi
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Patent number: 7423324Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.Type: GrantFiled: April 5, 2005Date of Patent: September 9, 2008Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Toshihiro Sekigawa, Yongxun Liu, Meishoku Masahara, Hanpei Koike, Eiichi Suzuki
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Patent number: 7382020Abstract: Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively.Type: GrantFiled: March 1, 2005Date of Patent: June 3, 2008Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Yongxun Liu, Toshihiro Sekigawa, Meishoku Masahara, Kenichi Ishii, Eiichi Suzuki
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Patent number: 7282959Abstract: It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.Type: GrantFiled: March 7, 2005Date of Patent: October 16, 2007Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Toshihiro Sekigawa, Hanpei Koike, Yongxun Liu, Meishoku Masahara
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Publication number: 20070029623Abstract: A dual-gate field effect transistor includes a substrate 1, a source 7-1, a drain 7-2, a vertical channel 5 provided between the source and the drain as rising from the substrate, a pair of gate insulation films 6-1 and 6-2 sandwiching the channel from a direction orthogonal to a carrier-running direction in the channel and a pair of gate electrodes 3-1 and 3-2 facing the vertical channel 5, respectively, via the pair of gate insulation films 6-1 and 6-2, wherein the pair of insulation films have different thicknesses t1 and t2. It is also possible that the pair of gate insulation films 6-1 and 6-2 have different permittivities ?1 and ?2 and that the pair of gate electrodes have different work functions ?1 and ?2. Thus, it is possible to set the threshold voltage of the dual-gate field effect transistor to a desired value when fabricating it. Furthermore, it is possible to avoid the problem of an increase in subthreshold slope that occurs in the prior art.Type: ApplicationFiled: December 6, 2004Publication date: February 8, 2007Applicant: National Inst of Adv Industrial Science and TechInventors: Yongxun Liu, Meishoku Masahara, Kenichi Ishii, Toshihiro Sekigawa, Eiichi Suzuki
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Publication number: 20050224884Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.Type: ApplicationFiled: April 5, 2005Publication date: October 13, 2005Inventors: Toshihiro Sekigawa, Yongxun Liu, Meishoku Masahara, Hanpei Koike, Eiichi Suzuki
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Publication number: 20050199919Abstract: Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively.Type: ApplicationFiled: March 1, 2005Publication date: September 15, 2005Inventors: Yongxun Liu, Toshihiro Sekigawa, Meishoku Masahara, Kenichi Ishii, Eiichi Suzuki
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Publication number: 20050199964Abstract: It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.Type: ApplicationFiled: March 7, 2005Publication date: September 15, 2005Inventors: Toshihiro Sekigawa, Hanpei Koike, Yongxun Liu, Meishoku Masahara
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Patent number: 6903637Abstract: The micro-switch couples electrically a first terminal to a second terminal. The micro-switch includes: a first supporting member where the first terminal is provided; a moving unit where the second terminal corresponding to the first terminal is provided; a driving unit for bringing the second terminal into contact with the first terminal by driving the moving unit in a direction of the first terminal by supplying power; an electrode provided in the first supporting member, and for supplying power to the driving unit; an elastic terminal including the elastic unit having elasticity in a predetermined direction; and a pushing terminal contacting the elastic terminal by pushing the elastic unit, the pushing terminal being electrically coupled to the electrode.Type: GrantFiled: December 26, 2002Date of Patent: June 7, 2005Assignee: Advantest CorporationInventors: Masaru Miyazaki, Hirokazu Sampei, Yongxun Liu, Masayoshi Esashi