Patents by Inventor Yoni Landau
Yoni Landau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11805042Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: GrantFiled: September 20, 2022Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Yoni Landau, Janardhan Satyanarayana, Assaf Benhamou, Mark Bordogna
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Patent number: 11711159Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.Type: GrantFiled: December 24, 2020Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Mark Bordogna, Janardhan Satyanarayana, Yoni Landau, Diwakar Suvvari
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Publication number: 20230016505Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: ApplicationFiled: September 20, 2022Publication date: January 19, 2023Applicant: Intel CorporationInventors: Yoni Landau, Janardhan Satyanarayana, Assaf Benhamou, Mark Bordogna
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Patent number: 11546241Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: GrantFiled: October 18, 2021Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna
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Publication number: 20220150149Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: ApplicationFiled: October 18, 2021Publication date: May 12, 2022Inventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf BENHAMOU, Mark A. Bordogna
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Patent number: 11265096Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.Type: GrantFiled: May 13, 2019Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Mark Bordogna, Janardhan Satyanarayana, Yoni Landau, Diwakar Suvvari
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Patent number: 11190208Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: GrantFiled: June 18, 2020Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Patent number: 11153191Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: GrantFiled: March 30, 2018Date of Patent: October 19, 2021Assignee: Intel CorporationInventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna
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Publication number: 20210152271Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.Type: ApplicationFiled: December 24, 2020Publication date: May 20, 2021Inventors: Mark BORDOGNA, Janardhan SATYANARAYANA, Yoni LANDAU, Diwakar SUVVARI
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Patent number: 10924132Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: GrantFiled: September 8, 2017Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Publication number: 20200321978Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Inventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Publication number: 20190273571Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.Type: ApplicationFiled: May 13, 2019Publication date: September 5, 2019Inventors: Mark BORDOGNA, Janardhan SATYANARAYANA, Yoni LANDAU, Diwakar SUVVARI
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Publication number: 20190215008Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: ApplicationFiled: September 8, 2017Publication date: July 11, 2019Applicant: Intel CorporationInventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Publication number: 20190044839Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.Type: ApplicationFiled: March 30, 2018Publication date: February 7, 2019Inventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna
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Patent number: 9722717Abstract: Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.Type: GrantFiled: December 18, 2014Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Yoni Landau, Assaf Benhamou, Adee O. Ran
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Publication number: 20160182175Abstract: Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Yoni Landau, Assaf Benhamou, Adee O. Ran