Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A touch screen panel includes a substrate, a plurality of touch electrodes in a touch area of the substrate, the touch electrodes sensing a touch, a connection line connected to a touch electrode of the plurality of touch electrodes, and a pad connected to one end of the connection line. The pad includes a first pad, a second pad on the first pad within a boundary line of the first pad, and a third pad covering a top surface and a side surface of the second pad.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: An organic light emitting diode display having a lightly doped region formed in a transistor for simplifying manufacturing process and reducing manufacturing costs is provided. The organic light emitting diode display includes: a substrate, a transistor on the substrate, and an organic light emitting diode (OLED) connected to the transistor, wherein the transistor includes a semiconductor member on the substrate, an insulating member on the semiconductor member, a source member and a drain member disposed on the semiconductor member and respectively disposed at opposite sides of the insulating member, and a gate electrode on the insulating member, wherein each of the source member and the drain member includes a plurality of layers having different impurity doping concentrations.

Abstract: A thin film transistor includes a semiconductor pattern formed on a substrate, the semiconductor pattern being formed of an oxide semiconductor and including a source area, a drain area, and an intermediate area that is formed between the source area and the drain area and includes a plurality of first areas and a second area having higher conductivity than the first areas; a first insulating pattern formed to cover at least the first areas; a second insulating film formed to face the second area, the source area and the drain area; a gate electrode formed on the semiconductor pattern and insulated from the semiconductor pattern by the first insulating pattern and the second insulating film; and source and drain electrodes insulated from the gate electrode and being in contact with the source area and the drain area.

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A thin film transistor substrate includes the following elements: a base substrate, a data line disposed on the base substrate, a source electrode contacting the data line, a drain electrode spaced from the source electrode, a channel disposed between the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a gate insulation pattern disposed on the channel, and a gate electrode disposed on the gate insulation pattern.

Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

Abstract: A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides. The TFT also comprises source and drain regions formed at the opposing sides of the active layer, a first insulating layer formed over the active layer, a gate electrode formed over the active layer, a second insulating layer formed covering the first insulation layer and the gate electrode, and a first conductive layer formed on the source and drain regions and contacting the second insulating layer.

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.

Abstract: A blind display device includes a plurality of curved display panels, a support, and a plurality of rotators. Each of the curved display panels includes a curved display area between a flat display area and a bezel area. The support guides movement of the curved display panels. The rotators couple corresponding ones of the curved display panels to the support and rotate corresponding ones of the curved display panels.

Abstract: A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides. The TFT also comprises source and drain regions formed at the opposing sides of the active layer, a first insulating layer formed over the active layer, a gate electrode formed over the active layer, a second insulating layer formed covering the first insulation layer and the gate electrode, and a first conductive layer formed on the source and drain regions and contacting the second insulating layer.

Abstract: A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A touch screen panel includes a substrate, a plurality of touch electrodes in a touch area of the substrate, the touch electrodes sensing a touch, a connection line connected to a touch electrode of the plurality of touch electrodes, and a pad connected to one end of the connection line. The pad includes a first pad, a second pad on the first pad within a boundary line of the first pad, and a third pad covering a top surface and a side surface of the second pad.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A lenticular unit includes a transparent substrate; first electrodes being transparent and disposed on the substrate; a second electrode being transparent and elastic; and a transparent material layer interposed between the first and second electrodes and being deformable in a lens shape in a thickness direction depending on a potential applied between the first and second electrodes.

Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.