Abstract: Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.

Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.

Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.

Abstract: Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.

Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

Abstract: In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.

Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

Abstract: A method of forming a phase change memory device includes forming a core pattern on a substrate, conformally forming a heat conductive layer on the substrate including the core pattern, anisotropically etching the heat conductive layer down to a top surface of the core pattern to form a heat electrode surrounding a sidewall of the core pattern, and forming a phase change memory pattern connected to a top surface of the heat electrode.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.

Abstract: A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

Abstract: Provided is a phase change memory device and a method of manufacturing the phase change memory device. In the phase change memory device, since a flat surface of a buffer pattern and a lower electrode are stably in contact with each other in a center of a recess, a resistance of a contact surface between the lower electrode and the buffer pattern can be minimized and thereby the phase change memory device can be operated by a small current. Since a method of manufacturing the phase change memory device needs one time etching process to form a recess exposing a semiconductor substrate to an insulating layer until forming a lower electrode after forming a device isolation layer, it is very economical.

Abstract: A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another.

Abstract: A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.