Abstract: A display unit including a liquid crystal layer, a plurality of optical layers and an imaging device. The imaging device is aligned to a portion of the display unit, the portion configured to transmit more than 10% of light rays to the imaging device. A method of assembling the same is also provided.

Abstract: A transmitter device may communicate with a receiver device via one or more data links. Data transmitted over the data links may be conveyed in accordance with a communications protocol that requires a deterministic latency for all data lanes in each of the data links. The receiver device may include a deterministic latency controller configured to store a worst-case latency value acquired upon initial startup and a predetermined link reinitialization latency compensation value. During normal operation, the deterministic latency controller may sum together the worst-case latency value and the predetermined link reinitialization latency compensation value to obtain a total compensated deterministic latency that is applied to all data links for simultaneous data release.

Abstract: A FIFO may use lookahead circuitry to boost performance and reduce data transfer latency by reducing the FIFO operation cycles when operating in the store and forward mode. The lookahead circuitry may increase data transfer rate of the FIFO between two integrated circuit devices that use different clock frequencies. The use of the lookahead circuitry with the FIFO may also reduce power consumption of the FIFO, allow storage media of the FIFO to be smaller, and free up valuable die space for other circuitry.

Abstract: The present application is directed to an electronic device that has a receiver configured to receive data from a second electronic device and identify potential sync header locations within a portion of the data by performing a mutually exclusive or (XOR) logic operation on a plurality of sequential pairs of bits of the data. Additionally, the receiver is configured to identify sync headers in the data by determining which of the potential sync header locations is shared in subsequent portions of the data.

Abstract: The present application is directed to an electronic device that has a receiver configured to receive data from a second electronic device and identify potential sync header locations within a portion of the data by performing a mutually exclusive or (XOR) logic operation on a plurality of sequential pairs of bits of the data. Additionally, the receiver is configured to identify sync headers in the data by determining which of the potential sync header locations is shared in subsequent portions of the data.

Abstract: A transmitter device may communicate with a receiver device via one or more data links. Data transmitted over the data links may be conveyed in accordance with a communications protocol that requires a deterministic latency for all data lanes in each of the data links. The receiver device may include a deterministic latency controller configured to store a worst-case latency value acquired upon initial startup and a predetermined link reinitialization latency compensation value. During normal operation, the deterministic latency controller may sum together the worst-case latency value and the predetermined link reinitialization latency compensation value to obtain a total compensated deterministic latency that is applied to all data links for simultaneous data release.

Abstract: Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.

Abstract: A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices.

Abstract: Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The frequency-divided signal is delayed in order to generate two signals that are phase shifted from one another by 90 degrees. These signals are then exclusive-ORed together to generate a recovered clock. A control loop is provided to adjust the phase shift between the signals to be approximately 90 degrees.

Abstract: Method and apparatus are provided for a synchronising execution of a plurality of threads on a multi-threaded processor. Each thread is provided with a number of synchronisation points corresponding to points where it is advantageous or preferable that execution should be synchronised with another thread. Execution of a thread is paused when it reaches a synchronisation point until at least one other thread with which it is intended to be synchronised reaches a corresponding synchronisation point. Execution is subsequently resumed. Where an executing thread branches over a section of code which included a synchronisation point then execution is paused at the end of the branch until the at least one other thread reaches the synchronisation point of the end of the corresponding branch.