Patents by Inventor Yoongoo KANG
Yoongoo KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230354587Abstract: A semiconductor device includes an active region; an isolation region on a side surface of the active region; a gate trench intersecting the active region and extending into the isolation region; a gate structure in the gate trench; a first impurity region and a second impurity region in the active region on both sides of the gate structure and spaced apart from each other; a bit line structure including a line portion intersecting the gate structure and a plug portion below the line portion and electrically connected to the first impurity region; and an insulating structure on a side surface of the plug portion. The insulating structure includes a spacer including a first material; an insulating pattern between the plug portion and the spacer and including a second material; and an insulating liner covering a side surface and a bottom surface of the insulating pattern and including a third material.Type: ApplicationFiled: April 21, 2023Publication date: November 2, 2023Inventors: Yoongoo Kang, Sangyoon Oh, Wonseok Yoo, Kyeongock Chong, Haeseul Kang
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Publication number: 20230292491Abstract: A semiconductor device may include contact plug structures on a substrate, and an insulation structure filling a space between the contact plug structures to insulate the contact plug structures from each other. The contact plug structures may be spaced apart from each other in a first direction. The insulation structure may include a first insulation pattern and a second insulation pattern. The second insulation pattern may include an insulation material having an etch selectivity with respect to silicon oxide. The first insulation pattern may contact a portion of sidewalls of the second insulation pattern and a portion of sidewalls of the contact plug structure. The first insulation pattern may include a material having a band gap higher than a band gap of the second insulation pattern.Type: ApplicationFiled: December 28, 2022Publication date: September 14, 2023Inventors: Kyungwook Park, Sangmin Kang, Yoongoo Kang, Changwoo Seo, Suyoun Song, Dain Lee
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Patent number: 11729966Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.Type: GrantFiled: April 18, 2022Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoongoo Kang, Wonseok Yoo, Hokyun An, Kyungwook Park, Dain Lee
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Publication number: 20220246620Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.Type: ApplicationFiled: April 18, 2022Publication date: August 4, 2022Inventors: Yoongoo KANG, Wonseok YOO, Hokyun AN, Kyungwook PARK, Dain LEE
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Patent number: 11335689Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.Type: GrantFiled: April 1, 2020Date of Patent: May 17, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoongoo Kang, Wonseok Yoo, Hokyun An, Kyungwook Park, Dain Lee
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Publication number: 20220093387Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.Type: ApplicationFiled: April 5, 2021Publication date: March 24, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Dain LEE, Yoongoo KANG, Wonseok YOO, Jinwon MA, Kyungwook PARK, Changwoo SEO, Suyoun SONG
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Patent number: 11177215Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.Type: GrantFiled: February 27, 2020Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungwook Park, Yoongoo Kang, Wonseok Yoo, Dain Lee
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Patent number: 11037991Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.Type: GrantFiled: April 23, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoongoo Kang, Changwoo Seo, Dain Lee, Wook-Yeol Yi, Hoi Sung Chung
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Publication number: 20210066304Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.Type: ApplicationFiled: April 1, 2020Publication date: March 4, 2021Inventors: Yoongoo KANG, Wonseok YOO, Hokyun AN, Kyungwook PARK, Dain LEE
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Publication number: 20210066200Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.Type: ApplicationFiled: February 27, 2020Publication date: March 4, 2021Inventors: Kyungwook Park, Yoongoo Kang, Wonseok Yoo, Dain Lee
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Publication number: 20200105832Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.Type: ApplicationFiled: April 23, 2019Publication date: April 2, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: YOONGOO KANG, CHANGWOO SEO, DAIN LEE, WOOK-YEOL YI, HOI SUNG CHUNG
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Patent number: 8853660Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.Type: GrantFiled: November 5, 2012Date of Patent: October 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: JaeJong Han, Sungun Kwon, Jinhye Bae, Kongsoo Lee, Seong Hoon Jeong, Yoongoo Kang, Ho-Kyun An
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Publication number: 20140120685Abstract: A semiconductor device and method of forming a semiconductor device is disclosed. The method includes forming a first ion-implanted layer having an amorphous state in a substrate; forming an impurity region of a first conductive type in the substrate; forming a semiconductor pattern on the substrate; forming a first doped region of the first conductive type in the semiconductor pattern; and forming a second doped region of a second conductive type contrary to the first conductive type in the semiconductor pattern. The first ion-implanted layer is formed by implanting carbons ions or germanium ions in the substrate.Type: ApplicationFiled: March 8, 2013Publication date: May 1, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong Hoon JEONG, Yoongoo KANG, Ho-Kyun AN, KONGSOO LEE, JAEJONG HAN