Patents by Inventor YOONKYEONG JO

YOONKYEONG JO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including via and wiring
    Patent number: 11637065
    Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ? of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ? of the width of the top surface of the via.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: April 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Miji Lee, Taeyoung Jeong, Yoonkyeong Jo, Sangwoo Pae, Hwasung Rhee
  • SEMICONDUCTOR DEVICE INCLUDING VIA AND WIRING
    Publication number: 20220148965
    Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ? of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ? of the width of the top surface of the via.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Inventors: MIJI LEE, TAEYOUNG JEONG, YOONKYEONG JO, SANGWOO PAE, HWASUNG RHEE
  • Semiconductor device including via and wiring
    Patent number: 11239162
    Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ? of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ? of the width of the top surface of the via.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Miji Lee, Taeyoung Jeong, Yoonkyeong Jo, Sangwoo Pae, Hwasung Rhee
  • SEMICONDUCTOR DEVICE INCLUDING VIA AND WIRING
    Publication number: 20210043556
    Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ? of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ? of the width of the top surface of the via.
    Type: Application
    Filed: May 19, 2020
    Publication date: February 11, 2021
    Inventors: MIJI LEE, TAEYOUNG JEONG, YOONKYEONG JO, SANGWOO PAE, HWASUNG RHEE