Patents by Inventor Yorai Itzhak Zack

Yorai Itzhak Zack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230376450
    Abstract: A method for processing includes receiving a definition of a processing pipeline including multiple sequential processing stages. The processing pipeline is partitioned into a plurality of partitions. The first partition of the processing pipeline is executed on a first computational accelerator, whereby the first computational accelerator writes output data from a final stage of the first partition to an output buffer in a first memory. The output data are copied over a packet communication network to an input buffer in a second memory. The second partition of the processing pipeline is executed on a second computational accelerator using the copied output data in the second memory as input data to a first stage of the second partition.
    Type: Application
    Filed: September 14, 2022
    Publication date: November 23, 2023
    Inventors: Adit Ranadive, Omri Kahalon, Aviad Shaul Yehezkel, Liran Liss, Gal Shalom, Yorai Itzhak Zack, Tushar Khinvasara
  • Patent number: 11792139
    Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: October 17, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Boris Pismenny, Ben Ben Ishay, Gal Yefet, Gil Kremer, Avi Urman, Yorai Itzhak Zack, Khalid Manaa, Liran Liss
  • Patent number: 11726666
    Abstract: A network adapter includes a network interface controller and a processor. The network interface controller is to communicate over a peripheral bus with a host, and over a network with a remote storage device. The processor is to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive first I/O transactions of the bus storage protocol from the host, via the exposed peripheral-bus device, and to complete the first I/O transactions in the remote storage device by (i) translating between the first I/O transactions and second I/O transactions of a network storage protocol, and (ii) executing the second I/O transactions in the remote storage device. For receiving and completing the first I/O transactions, the processor is to cause the network interface controller to transfer data directly between the remote storage device and a memory of the host using zero-copy.
    Type: Grant
    Filed: July 11, 2021
    Date of Patent: August 15, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ben Ben-Ishay, Boris Pismenny, Yorai Itzhak Zack, Khalid Manaa, Liran Liss, Uria Basher, Or Gerlitz, Miriam Menes
  • Publication number: 20230239257
    Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 27, 2023
    Inventors: Boris Pismenny, Ben Ben Ishay, Gal Yefet, Gil Kremer, Avi Urman, Yorai Itzhak Zack, Khalid Manaa, Liran Liss
  • Publication number: 20230010150
    Abstract: A network adapter includes a network interface controller and a processor. The network interface controller is to communicate over a peripheral bus with a host, and over a network with a remote storage device. The processor is to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive first I/O transactions of the bus storage protocol from the host, via the exposed peripheral-bus device, and to complete the first I/O transactions in the remote storage device by (i) translating between the first I/O transactions and second I/O transactions of a network storage protocol, and (ii) executing the second I/O transactions in the remote storage device. For receiving and completing the first I/O transactions, the processor is to cause the network interface controller to transfer data directly between the remote storage device and a memory of the host using zero-copy.
    Type: Application
    Filed: July 11, 2021
    Publication date: January 12, 2023
    Inventors: Ben Ben-Ishay, Boris Pismenny, Yorai Itzhak Zack, Khalid Manaa, Liran Liss, Uria Basher, Or Gerlitz, Miriam Menes