Patents by Inventor Yoram Betser
Yoram Betser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10304545Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: GrantFiled: June 1, 2018Date of Patent: May 28, 2019Assignee: Cypress Semiconductor CorporationInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Patent number: 10305461Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.Type: GrantFiled: June 22, 2017Date of Patent: May 28, 2019Assignee: Cypress Semiconductor CorporationInventors: Alexander Kushnarenko, Yoram Betser
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Patent number: 10229745Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.Type: GrantFiled: January 23, 2018Date of Patent: March 12, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Publication number: 20190035477Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: ApplicationFiled: June 1, 2018Publication date: January 31, 2019Applicant: Cypress Semiconductor CorporationInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Patent number: 10192627Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: GrantFiled: April 17, 2018Date of Patent: January 29, 2019Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
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Patent number: 10147734Abstract: A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the third signal are received concurrently.Type: GrantFiled: March 19, 2018Date of Patent: December 4, 2018Assignee: Cypress Semiconductor CorporationInventors: Roni Varkony, Yoram Betser
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Patent number: 10141065Abstract: A semiconductor device comprises an embedded flash memory with row redundancy. The embedded flash memory comprises a memory bank that includes multiple physical sectors, where each physical sector comprises a plurality of erase sectors. In the memory bank, multiple portions of an additional erase sector are respectively distributed among the multiple physical sectors. The multiple portions of the additional erase sector are configured as a row-redundancy sector for the memory bank.Type: GrantFiled: December 21, 2017Date of Patent: November 27, 2018Assignee: Cypress Semiconductor CorporationInventors: Kobi Danon, Yoram Betser, Uri Kotlicki, Arieh Feldman
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Publication number: 20180261295Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: ApplicationFiled: April 17, 2018Publication date: September 13, 2018Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai GIVANT, Shivananda Shetty, Shenqing Fang
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Patent number: 10043555Abstract: Disclosed is a method for responding to a single user read command of a complementary cell array including one or more complementary cell pairs, the method including: determining if a first group of cells out of a data word is in an erased state or in a programmed state, and outputting a data word so that (a) if the first group of cells is determined to be erased a logical “one” is output for each bit of the data word and (b) if the first group of cells is determined to be programmed the result of a complementary read is output for each bit of the data word.Type: GrantFiled: July 11, 2017Date of Patent: August 7, 2018Assignee: Cypress Semiconductor CorporationInventors: Kobi Danon, Yoram Betser, Alex Kushnarenko
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Publication number: 20180190361Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.Type: ApplicationFiled: January 23, 2018Publication date: July 5, 2018Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Publication number: 20180166141Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: ApplicationFiled: March 28, 2017Publication date: June 14, 2018Applicant: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo-Tung Chang, Amichai GIVANT, Shivananda SHETTY, Shenqing Fang
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Patent number: 9997253Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.Type: GrantFiled: March 28, 2017Date of Patent: June 12, 2018Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Yoram Betser, Kuo-Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
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Patent number: 9991001Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.Type: GrantFiled: May 22, 2014Date of Patent: June 5, 2018Assignee: Cypress Semiconductor CorporationInventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
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Publication number: 20180131358Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.Type: ApplicationFiled: June 22, 2017Publication date: May 10, 2018Inventors: Alexander Kushnarenko, Yoram Betser
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Patent number: 9881683Abstract: Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.Type: GrantFiled: April 25, 2017Date of Patent: January 30, 2018Assignee: Cypress Semiconductor CorporationInventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
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Publication number: 20170365300Abstract: Disclosed is a method for responding to a single user read command of a complementary cell array including one or more complementary cell pairs, the method including: determining if a first group of cells out of a data word is in an erased state or in a programmed state, and outputting a data word so that (a) if the first group of cells is determined to be erased a logical “one” is output for each bit of the data word and (b) if the first group of cells is determined to be programmed the result of a complementary read is output for each bit of the data word.Type: ApplicationFiled: July 11, 2017Publication date: December 21, 2017Applicant: Cypress Semiconductor CorporationInventors: Kobi Danon, Yoram Betser, Alex Kushnarenko
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Patent number: 9773529Abstract: A method for operating a read command of N complementary memory cells, the method includes the steps of determining if each of the first and second memory cells of the N complementary memory cells is in a first binary state or a second binary state, generating a count value by counting a total number of the first and second memory cells that are in the first binary state, and determining if the N complementary memory cells are programmed or erased based on a result of comparing the count value to a threshold number.Type: GrantFiled: September 29, 2016Date of Patent: September 26, 2017Assignee: Cypress Semiconductor CorporationInventors: Kobi Danon, Yoram Betser, Alex Kushnarenko
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Patent number: 9479171Abstract: Disclosed is an integrated circuit voltage level shifter including: a first set of pull-up transistors to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on the input and a third set of transistors to limit current flow through the second set of pull-down transistors and to mitigate snapback of the second set of pull-down transistors using a bias gate voltage.Type: GrantFiled: May 22, 2014Date of Patent: October 25, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Roni Varkony, Yoram Betser
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Publication number: 20150341023Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: Spansion LLCInventors: Alexander Kushnarenko, Yoram Betser
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Publication number: 20150341034Abstract: Disclosed is an integrated circuit voltage level shifter including: a first set of pull-up transistors to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on the input and a third set of transistors to limit current flow through the second set of pull-down transistors and to mitigate snapback of the second set of pull-down transistors using a bias gate voltage.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: Spansion LLCInventors: Roni Varkony, Yoram Betser