Patents by Inventor YoRim Lee

YoRim Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8143103
    Abstract: A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 27, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Young-Joon Kim, YoRim Lee
  • Publication number: 20110121465
    Abstract: A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Inventors: YoungJoon Kim, YoRim Lee
  • Patent number: 7898072
    Abstract: A package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 1, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: YoungJoon Kim, YoRim Lee
  • Patent number: 7875495
    Abstract: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: January 25, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: TaeWoo Kang, YoRim Lee, TaeKeun Lee
  • Patent number: 7682872
    Abstract: An integrated circuit package system includes: providing a package carrier; forming a first channel in the package carrier; mounting a first integrated circuit device over the package carrier and adjacent to the first channel; mounting a second integrated circuit device over the package carrier and adjacent to the first channel; and forming a contiguous underfill fillet with the first channel and under both the first integrated circuit device and the second integrated circuit device.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: March 23, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: SooMoon Park, Tae Keun Lee, YoRim Lee
  • Publication number: 20100022050
    Abstract: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.
    Type: Application
    Filed: September 30, 2009
    Publication date: January 28, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: TaeWoo Kang, YoRim Lee, TaeKeun Lee
  • Publication number: 20100007000
    Abstract: A package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 14, 2010
    Inventors: YoungJoon Kim, YoRim Lee
  • Patent number: 7615865
    Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: November 10, 2009
    Assignee: STATS ChipPAC, Ltd.
    Inventors: TaeWoo Kang, YoRim Lee, TaeKeun Lee
  • Publication number: 20080293232
    Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 27, 2008
    Applicant: STATS CHIPPAC, LTD.
    Inventors: TaeWoo KANG, YoRim LEE, TaeKeun LEE
  • Publication number: 20080211111
    Abstract: An integrated circuit package system includes: providing a package carrier; forming a first channel in the package carrier; mounting a first integrated circuit device over the package carrier and adjacent to the first channel; mounting a second integrated circuit device over the package carrier and adjacent to the first channel; and forming a contiguous underfill fillet with the first channel and under both the first integrated circuit device and the second integrated circuit device.
    Type: Application
    Filed: February 25, 2008
    Publication date: September 4, 2008
    Inventors: SooMoon Park, Tae Keun Lee, YoRim Lee