Patents by Inventor Yorinobu FUJINO
Yorinobu FUJINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038296Abstract: A memory device is provided, including a first word line coupled to a first memory cell, a second word line coupled to a second memory cell, and a read assist circuit coupled between the first and second word lines, and in a first time period configured, in response to a first control signal, to adjust a voltage level of the first word line to a first voltage and to adjust a voltage level of the second word line to a second voltage. In some embodiments, the first voltage is smaller than a first supply voltage, and the second voltage is greater than a second supply voltage smaller than the first supply voltage.Type: ApplicationFiled: July 26, 2022Publication date: February 1, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Yorinobu FUJINO
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Publication number: 20240021241Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a drive circuit coupled to a first line and a second line. In one aspect, the drive circuit is configured to apply, according to a first control signal having a first state, a data signal to either one of the first line or the second line to write data at a memory cell. In one aspect, the memory device includes a pre-charge circuit configured to set, according to a second control signal having a second state, voltages at the first line and the second line to a predetermined voltage level. In one aspect, the memory device includes an equalizer configured to electrically decouple the first line from the second line, according to the first control signal having the first state and the second control signal having the second state.Type: ApplicationFiled: January 30, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Masaru Haraguchi, Yoshisato Yokoyama, Yorinobu Fujino
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Publication number: 20230037885Abstract: Disclosed herein is a sense amplifier. In one aspect, the sense amplifier includes a first pair of cross-coupled transistors and a second pair of cross-coupled transistors coupled to a first port and a second port of the sense amplifier. In one aspect, the sense amplifier includes a first access transistor coupled between a first input line and the first port. In one aspect, the sense amplifier includes a second access transistor coupled between a second input line and the second port. In one aspect, the first pair of cross-coupled transistors includes a first transistor and a second transistor cross-coupled with each other. In one aspect, a source electrode of the first transistor is directly coupled to the first input line, and a source electrode of the second transistor is directly coupled to the second input line.Type: ApplicationFiled: January 28, 2022Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yorinobu Fujino
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Patent number: 11145346Abstract: According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.Type: GrantFiled: March 11, 2020Date of Patent: October 12, 2021Assignee: KIOXIA CORPORATIONInventor: Yorinobu Fujino
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Patent number: 11127448Abstract: According to one embodiment, a memory device includes a resistance change memory element to which one of a low-resistance state and a high-resistance state is allowed to be set in accordance with a write current, a first transistor including a first gate, and causing a current to flow through the resistance change memory element in a first write period, a voltage holding section holding a first voltage applied to the first gate in the first write period, and a second transistor including a second gate, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the resistance change memory element in a second write period after the first write period.Type: GrantFiled: March 12, 2020Date of Patent: September 21, 2021Assignee: KIOXIA CORPORATIONInventor: Yorinobu Fujino
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Publication number: 20210090628Abstract: According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.Type: ApplicationFiled: March 11, 2020Publication date: March 25, 2021Applicant: KIOXIA CORPORATIONInventor: Yorinobu FUJINO
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Patent number: 10956092Abstract: A semiconductor storage device comprises first and second memory cells each including a variable-resistance element, a write driver, and a control circuit that concurrently performs an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data including a first write operation for a first time length and the operation to read the second data including a second write operation for a second time length. In the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length. In the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.Type: GrantFiled: February 26, 2020Date of Patent: March 23, 2021Assignee: KIOXIA CORPORATIONInventors: Yorinobu Fujino, Kosuke Hatsuda
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Publication number: 20210082486Abstract: According to one embodiment, a memory device includes a resistance change memory element to which one of a low-resistance state and a high-resistance state is allowed to be set in accordance with a write current, a first transistor including a first gate, and causing a current to flow through the resistance change memory element in a first write period, a voltage holding section holding a first voltage applied to the first gate in the first write period, and a second transistor including a second gate, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the resistance change memory element in a second write period after the first write period.Type: ApplicationFiled: March 12, 2020Publication date: March 18, 2021Applicant: KIOXIA CORPORATIONInventor: Yorinobu FUJINO
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Publication number: 20200364002Abstract: A semiconductor storage device comprises first and second memory cells each including a variable-resistance element, a write driver, and a control circuit that concurrently performs an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data including a first write operation for a first time length and the operation to read the second data including a second write operation for a second time length. In the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length. In the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.Type: ApplicationFiled: February 26, 2020Publication date: November 19, 2020Inventors: Yorinobu FUJINO, Kosuke HATSUDA
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Patent number: 10431277Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.Type: GrantFiled: September 13, 2017Date of Patent: October 1, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kosuke Hatsuda, Yorinobu Fujino
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Patent number: 10388345Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.Type: GrantFiled: March 12, 2018Date of Patent: August 20, 2019Assignee: TOSHIBA MEMORY CORORATIONInventors: Kosuke Hatsuda, Yoshiaki Osada, Yorinobu Fujino, Jieyun Zhou
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Patent number: 10338835Abstract: According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.Type: GrantFiled: March 13, 2017Date of Patent: July 2, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoshiaki Osada, Katsuhiko Hoya, Yorinobu Fujino, Kosuke Hatsuda
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Publication number: 20190088298Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.Type: ApplicationFiled: March 12, 2018Publication date: March 21, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kosuke HATSUDA, Yoshiaki OSADA, Yorinobu FUJINO, Jieyun ZHOU
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Patent number: 10157655Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.Type: GrantFiled: September 13, 2017Date of Patent: December 18, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yorinobu Fujino, Kosuke Hatsuda, Yoshiaki Osada
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Publication number: 20180277186Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.Type: ApplicationFiled: September 13, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kosuke HATSUDA, Yorinobu FUJINO
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Publication number: 20180277188Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.Type: ApplicationFiled: September 13, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yorinobu FUJINO, Kosuke HATSUDA, Yoshiaki OSADA
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Publication number: 20180074737Abstract: According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.Type: ApplicationFiled: March 13, 2017Publication date: March 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yoshiaki OSADA, Katsuhiko HOYA, Yorinobu FUJINO, Kosuke HATSUDA