Patents by Inventor Yorinobu Kunimune
Yorinobu Kunimune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230116260Abstract: A resistor material including a plurality of crystalline phases having a positive temperature coefficient of resistance, and an amorphous phase having a negative temperature coefficient of resistance and having a resistivity higher than the crystalline phase, in a mixed state, is provided. Moreover, a resistor element having a resistor film configured by the resistor material described above, and a method of manufacturing a resistor element by forming a film of an amorphous material having a negative temperature coefficient of resistance and subjecting this film to an annealing treatment to obtain the resistor element described above, are provided.Type: ApplicationFiled: August 22, 2022Publication date: April 13, 2023Inventors: Nozomi ITO, Yorinobu KUNIMUNE, Kenichiro ABE, Nobuhito SHIRAISHI
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Patent number: 10074740Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: GrantFiled: July 5, 2017Date of Patent: September 11, 2018Assignee: Renesas Electronics CorporationInventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20170301782Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: ApplicationFiled: July 5, 2017Publication date: October 19, 2017Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Patent number: 9722066Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: GrantFiled: February 28, 2016Date of Patent: August 1, 2017Assignee: Renesas Electronics CorporationInventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20160181411Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: ApplicationFiled: February 28, 2016Publication date: June 23, 2016Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Patent number: 9356110Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).Type: GrantFiled: February 5, 2014Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masao Inoue, Yoshiki Maruyama, Akio Nishida, Yorinobu Kunimune, Kota Funayama
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Patent number: 9293457Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: GrantFiled: July 15, 2015Date of Patent: March 22, 2016Assignee: Renesas Electronics CorporationInventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20160020207Abstract: To enhance electromigration resistance of an electrode. A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction). A recessed portion is located in a region overlapping with the drain electrode in a plan view. At least a part of the drain electrode is buried in the recessed portion. A side surface of the recessed portion, which faces the drain pad, enters the drain pad in the first direction (y direction).Type: ApplicationFiled: July 15, 2015Publication date: January 21, 2016Inventors: Hideaki Tsuchiya, Hiroshi Kimura, Takashi Ide, Yorinobu Kunimune
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Publication number: 20140312406Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).Type: ApplicationFiled: February 5, 2014Publication date: October 23, 2014Applicant: Renesas Electronics CorporationInventors: Masao INOUE, Yoshiki MARUYAMA, Akio NISHIDA, Yorinobu KUNIMUNE, Kota FUNAYAMA
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Patent number: 7846830Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.Type: GrantFiled: October 12, 2007Date of Patent: December 7, 2010Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune
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Patent number: 7687918Abstract: The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.Type: GrantFiled: December 22, 2003Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventors: Yorinobu Kunimune, Mieko Hasegawa, Takamasa Itou, Takeshi Takeda, Hidemitsu Aoki
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Publication number: 20080044997Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.Type: ApplicationFiled: October 12, 2007Publication date: February 21, 2008Inventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune
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Semiconductor device having an anti-oxidizing layer that inhibits corrosion of an interconnect layer
Patent number: 7312535Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.Type: GrantFiled: March 18, 2004Date of Patent: December 25, 2007Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune -
Patent number: 7309991Abstract: A pair of pads is formed on an insulating layer formed on a top surface of a substrate, and a plurality of through-holes is laid out at equal intervals between the pads. Adjoining through holes are connected alternately by upper-layer wire interconnect lines exposed on the insulating layer or lower-layer wire interconnect lines buried in the insulating layer, thus constituting a check pattern. A DC power supply is connected between the pair of pads, and a constant current is supplied to a chain pattern of the through holes. Two probes move on a chip surface along the chain pattern of the through holes while keeping a given interval spacing. The probes sequentially scan the upper-layer wire interconnect lines exposed through the chip surface of the chain pattern of the through-holes.Type: GrantFiled: September 29, 2003Date of Patent: December 18, 2007Assignee: NEC Electronics CorporationInventor: Yorinobu Kunimune
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Publication number: 20060119373Abstract: A pair of pads (1) are formed on an insulating layer formed on a top surface of a substrate, and a plurality of through-holes (2) are arrangedlaid out at equal intervalsintervals between the pads (1). The adjoining through holes (2) are connected alternately by upper-layer wireupper interconnect lines (4) exposed on the insulating layer or lower-layer wirelower interconnect lines (3) buried in the insulating layer, thus constituting a check pattern. A DC power supply (12) is connected between the pair of pads (1), and a constant current Io is supplied to a chain pattern of the through holes (2). Two probes (10) move on a chip surface along the chain pattern of the through holes (2) while keeping a given intervalspacing d. Accordingly, the probes (10) sequentially scan the upper-layer wireupper interconnect lines (4) exposed through the chip surface of the chain pattern of the through-holes (2).Type: ApplicationFiled: September 29, 2003Publication date: June 8, 2006Applicant: NEC ELECTRONICS CORPORATIONInventor: Yorinobu Kunimune
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Publication number: 20040188851Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.Type: ApplicationFiled: March 18, 2004Publication date: September 30, 2004Applicant: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune
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Publication number: 20040130030Abstract: The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.Type: ApplicationFiled: December 22, 2003Publication date: July 8, 2004Applicant: NEC Electronics CorporationInventors: Yorinobu Kunimune, Mieko Hasegawa, Takamasa Itou, Takeshi Takeda, Hidemitsu Aoki