Patents by Inventor Yoshiaki Hisamune

Yoshiaki Hisamune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6770533
    Abstract: Provided are a method of manufacturing a semiconductor, a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein: the memory device has a plurality of memory cells; a buried diffusion layer serves as a signal line; and, a buried diffusion layer disposed adjacent to each of opposite end portions of a lower floating gate is free from variations in width resulted from misalignment occurring in an optical aligner. In the memory device, for example: the floating gate is formed in an active region of a P-type semiconductor substrate through a gate oxide film; an N-type drain region and an N-type source region are formed in opposite end portions of the floating gate; and, a pair of device isolation shielding electrode extends in parallel with the floating gate outside both the drain region and the source region to cover adjacent ones of the memory cells.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: August 3, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Yoshiaki Hisamune, Hidetoshi Nakata
  • Publication number: 20020102794
    Abstract: Provided are a method of manufacturing a semiconductor, a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein: the memory device has a plurality of memory cells; a buried diffusion layer serves as a signal line; and, a buried diffusion layer disposed adjacent to each of opposite end portions of a lower floating gate is free from variations in width resulted from misalignment occurring in an optical aligner. In the memory device, for example: the floating gate is formed in an active region of a P-type semiconductor substrate through a gate oxide film; an N-type drain region and an N-type source region are formed in opposite end portions of the floating gate; and, a pair of device isolation shielding electrode extends in parallel with the floating gate outside both the drain region and the source region to cover adjacent ones of the memory cells.
    Type: Application
    Filed: February 27, 2002
    Publication date: August 1, 2002
    Applicant: NEC CORPORATION
    Inventors: Yoshiaki Hisamune, Hidetoshi Nakata
  • Patent number: 6373096
    Abstract: Provided are a method of manufacturing a semiconductor, a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein: the memory device has a plurality of memory cells; a buried diffusion layer serves as a signal line; and, a buried diffusion layer disposed adjacent to each of opposite end portions of a lower floating gate is free from variations in width resulted from misalignment occurring in an optical aligner. In the memory device, for example: the floating gate is formed in an active region of a P-type semiconductor substrate through a gate oxide film; an N-type drain region and an N-type source region are formed in opposite end portions of the floating gate; and, a pair of device isolation shielding electrode extends in parallel with the floating gate outside both the drain region and the source region to cover adjacent ones of the memory cells.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventors: Yoshiaki Hisamune, Hidetoshi Nakata
  • Patent number: 6172393
    Abstract: A nonvolatile memory includes a first conductive type of semiconductor region and a second conductive type of impurity diffusion layer. The impurity diffusion layer is formed by doping into a predetermined region of the semiconductor region, impurity of the second conductive type that differs from the first conductive type. The impurity diffusion layer is used as a bit line. The impurity diffusion layer has a specific layer in which an impurity density is substantially equal to or higher than 1×1018 cm−3, and wherein B>A where A is a diffusion length in a lateral direction from the predetermined region and B is a thickness of the specific layer in a depth direction.
    Type: Grant
    Filed: April 7, 1999
    Date of Patent: January 9, 2001
    Assignee: NEC Corporation
    Inventors: Kohji Kanamori, Yoshiaki Hisamune
  • Patent number: 5076204
    Abstract: An apparatus for producing semiconductor devices. A first automatic carrying system operates for taking from a lead frame tray a lead frame which mounts thereon semiconductor chips and for setting the lead frame on the suscepter. A thin film forming device operates for forming an insulating film on a surface of the lead frame disposed on the suscepter. A second automatic carrying system operates for taking from the suscepter the lead frame formed with the insulating film and for setting the lead frame into another lead frame tray. A transferring device operates for transferring the lead frame disposed on the suscepter from the first automatic carrying system through the thin film forming device to the second automatic carrying system.
    Type: Grant
    Filed: September 28, 1989
    Date of Patent: December 31, 1991
    Assignee: NEC Corporation
    Inventor: Yoshiaki Hisamune