Patents by Inventor Yoshiaki Katoh

Yoshiaki Katoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5247627
    Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
    Type: Grant
    Filed: August 27, 1991
    Date of Patent: September 21, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tokumichi Murakami, Koh Kamizawa, Yoshiaki Katoh, Hideo Ohira, Masatoshi Kameyama, Naoto Kinjo
  • Patent number: 5237667
    Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
    Type: Grant
    Filed: August 27, 1991
    Date of Patent: August 17, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tokumichi Murakami, Koh Kamizawa, Yoshiaki Katoh, Hideo Ohira, Masatoshi Kameyama, Naoto Kinjo
  • Patent number: 5222241
    Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
    Type: Grant
    Filed: August 27, 1991
    Date of Patent: June 22, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tokumichi Murakami, Koh Kamizawa, Yoshiaki Katoh, Hideo Ohira, Masatoshi Kameyama, Naoto Kinjo
  • Patent number: 5206940
    Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
    Type: Grant
    Filed: August 27, 1991
    Date of Patent: April 27, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tokumichi Murakami, Koh Kamizawa, Yoshiaki Katoh, Hideo Ohira, Masatoshi Kameyama, Naoto Kinjo
  • Patent number: 5049665
    Abstract: A cephalosporin derivative having the formula: ##STR1## wherein R.sup.1 is a substituted amino group, X is an alkylene group, R.sup.2 is an aryl or heterocyclic group which may be substituted and R.sup.3 is a hydrogen atom, a negative charge or a residue of an ester which can form a pharmaceutically acceptable ester hydrolyzable in a living body; or a pharmaceutically acceptable salt thereof.
    Type: Grant
    Filed: September 29, 1989
    Date of Patent: September 17, 1991
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Susumu Nakagawa, Hiroshi Fukatsu, Yoshiaki Katoh, Satoshi Murase
  • Patent number: 5045993
    Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
    Type: Grant
    Filed: June 3, 1988
    Date of Patent: September 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tokumichi Murakami, Koh Kamizawa, Yoshiaki Katoh, Hideo Ohira, Masatoshi Kameyama, Naoto Kinjo
  • Patent number: 4918070
    Abstract: A cephalosporin derivative having the formula: ##STR1## wherein R.sup.1 is a substituted amino group, X is an alkylene group, R.sup.2 is an aryl or heterocyclic group which may be substituted and R.sup.3 is a hydrogen atom, a negative charge or a residue of an ester which can form a pharmaceutically acceptable ester hydrolyzable in a living body; or a pharmaceutically acceptable salt thereof.
    Type: Grant
    Filed: February 26, 1988
    Date of Patent: April 17, 1990
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Susumu Nakagawa, Hiroshi Fukatsu, Yoshiaki Katoh, Satoshi Murase
  • Patent number: 4735068
    Abstract: A card operated lock includes a lock box in which an inner card slit opened to the interior of a room and a outer card slit opened to the exterior of the room are disposed in substantially coplanar relationship with each other. A lock card having a predetermined pattern of punched engaging holes is inserted previously into the inner card slit while a key card comprising the same pattern of punched engaging holes as the lock card is inserted into the outer card slit when the lock is unlocked or opened. A plurality of rocking tumblers each of which is substantially in the form of a T-shaped plate are inserted into the lock box in the form of an array extended in the widthwise direction of the key card and perpendicular to the card slits. A horizontal bar portion of each T-shaped rocking tumbler is extended along both the inner and outer card slits.
    Type: Grant
    Filed: March 12, 1987
    Date of Patent: April 5, 1988
    Assignee: Miwa Lock Co., Ltd.
    Inventors: Osamu Shimoi, Yoshiaki Katoh
  • Patent number: 4686286
    Abstract: A disazo reaction dyestuff for cellulose fibers which is of the formula: ##STR1## wherein D is a residue of a monoazo dye, R.sup.1 is hydrogen or lower alkyl, and X is a group: ##STR2## wherein R.sup.2 and R.sup.3 are each hydrogen, methyl, methoxy or --SO.sub.3 M, Y is an aromatic or aliphatic divalent residue and M is hydrogen or an alkali metal.
    Type: Grant
    Filed: May 17, 1985
    Date of Patent: August 11, 1987
    Assignee: Mitsubishi Chemical Industries Limited
    Inventors: Toshio Niwa, Yoshiaki Katoh
  • Patent number: 4561147
    Abstract: A door hinge of the type comprising a first metal plate having one vertical side edge formed integral with a pin and a second metal piece having one vertical side edge formed integral with a second knuckle cylinder into which is fitted the pin. A load plug is slideably fitted into the second knuckle cylinder for engagement with the upper end of the pin and the second knuckle cylinder is formed with an engaging portion for preventing the load plug from being displaced from a predetermined position. A compression spring means is loaded in the second knuckle cylinder above the load plug so as to press the load plug against the engaging portion, whereby a load applied axially to the pin is carried by the compression spring means through the load plug.
    Type: Grant
    Filed: December 22, 1983
    Date of Patent: December 31, 1985
    Assignee: Miwa Lock Co. Ltd.
    Inventors: Yoshiaki Katoh, Hiroshi Inuzuka
  • Patent number: 4256963
    Abstract: A linked scan type mass spectrometer wherein the mass number of a metastable ion originating from a precursor ion is measured by scanning the magnetic and electric fields at a constant ratio between the two fields. Calculation is performed on a first electrical signal representative of the mass number of the precursor ion, a second electrical signal corresponding to a value of the electric field at which the mass number of the precursor ion is detected, and a third electrical signal corresponding to a value of the electric field at which the metastable ion is detected during scanning of the electric field and magnetic field, to thereby determine the mass number of the metastable ion. The third electrical signal is obtained by measuring a value of the magnetic field which contributes to the dispersion of ions. Means is provided for correcting the measured value of the magnetic field, thereby determining the mass number of the metastable ion with high accuracy.
    Type: Grant
    Filed: September 28, 1979
    Date of Patent: March 17, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Sadao Takahashi, Yoshiaki Katoh