Abstract: The system is constructed to operate to mutually transfer information between a processor and a terminal device via a first-in/first-out type stack. Signal generators are provided on the input and output sides of the stack for generating signals corresponding to the EMPTY and FULL statuses of the stack thereby controlling to inhibit or commence the transfer of the information in response to the direction of transfer of the information and the status of the stack.

Abstract: A memory address designating system comprising a program counter and data counter for holding the addresses of an instruction word area and data area respectively of a memory, an increment/decrement counter for modifying the address, and gate circuits for controlling data transfer between the program counter, data counter and increment/decrement counter, in which, when the memory is accessed by the addresses of the instruction word area and data area of the memory, an address held in the program counter is modified by an increment/decrement counter and consequently is incremented by one and sent through a gate to the data counter where it is held. On the other hand, the address of the data area held in the data counter is supplied through a gate to he program counter and then to the increment/decrement counter where it is modified.

Abstract: Two flip-flops for carry information are provided in a data processor; one for carry of arithmetic operation and the other for carry occuring when a program counter is incremented. A state of the latter flip-flop provides a condition of a conditional branch instruction. With the provision of those flip-flops, a multidigit operation can be performed without increasing programsteps to save carry information attendant on the operation data. A simple program may be prepared without increasing hardware for skip instruction processing.

Abstract: A read only memory comprises a P-type substrate and a plurality of N.sup.+ -type diffusion layers arranged checkerwise on one major surface of the substrate in which four N.sup.+ -type diffusion layers having contacts are located at corners of an imaginary rectangle, and a fifth N.sup.+ -type region having a contact is formed substantially at the center of the imaginary rectangle. Between the fifth N.sup.+ -type diffusion layer and the first to fourth N.sup.+ -type diffusion layers four MOS transistors are formed for the single contact. Gate lines are provided, each extending between adjacent two N.sup.+ -type diffusion layers without overlapping them. Each of the four N.sup.+ -type diffusion layers also acts as a central N.sup.+ -type region of another imaginary rectangle adjacent to the first mentioned imaginary rectangle.

Abstract: The system comprises a central information processing unit, an input/output unit, a first-in first-out stack which is connected to receive information from the central information processing unit for sending a "FULL" signal to the central information processing unit when the stack is filled with the information sent from the central information processing unit and for sending thereto an "EMPTY" signal when the stack is empty, an input/output control circuit which operates to transfer the information from the first-in first-out stack to the input/output unit and to detect the state thereof for sending a "READY" signal to the central processing unit when the input/output unit is in a state ready for accepting the information, a command register coupled to the central information processing unit to be set at a particular bit by a bit signal sent from the central processing unit when it receives the "FULL" signal from the first-in first-out stack and the "READY" signal from the input/output control circuit, and a

Abstract: An information transfer control system for controlling the information transfer between a data processor and an input/output device is disposed between the data processor and the input/output device. The information transfer control system comprises a first-in/first-out stack for temporarily storing transferring information being transferred, an up/down counter with a preset function for selectively designating the address lines desired of the stack through a decoder, and a register for setting up a counting range of the counter. The addressing range data to be counted in the up/down counter is initialized in the up/down counter through a program.

Abstract: An information transferring apparatus disposed between first and second information processing units comprises a first-in first-out stack, a first information line for transferring information from the first information processing unit to the first-in first-out stack, a second information line for transferring information from the first-in first-out stack to the second information processing unit, a third information line for transferring information from the second information processing unit to the first-in first-out stack, a fourth information line for transferring information from the first-in first-out stack to the first information processing unit, switching circuits for selectively deactivating the first to fourth information lines, and a command register for applying first and second control signals to the switching circuits, wherein the switching circuits operate responsive to the first control signal from the command register to deactivate the third and fourth information lines while holding active

Abstract: In an information processing system comprising a central processing unit, an input/output unit and a first-in first-out stack connected between these units there are provided a buffer control circuit for detecting the full and empty states of the first-in first-out stack, an input/output control circuit connected between the first-in first-out stack and the input/output unit for detecting a predetermined state of the input/output unit, a status register for storing specific states of the first-in first-out stack and the input/output unit, a command register controlled by programmed information from the central processing unit for establishing a specific interruption condition corresponding to the specific states of the first-in first-out stack and the input/output unit, and an interruption control circuit coupled to the status register and the command register for applying an interruption signal to the central processing unit when the state signal from the status register and the interruption condition signal