Abstract: Wireless line termination units 21 and 22 respectively transmit and receive frames via wireless lines 51 and 52. Line termination units 25 and 26 respectively exchange frames with the wireless line termination units 21 and 22. The wireless lines 51 and 52 are treated as one virtual line. A radio monitoring unit 272 monitors the state of the wireless lines 51 and 52, and in accordance with the redundancy mode, instructs the wireless line termination units 21 and 22 to exchange copy frames with other wireless line termination unit and to abandon received frames. A communication path control unit 273 sets, in accordance with the monitoring result as to the state of the wireless lines by the radio monitoring unit 272, the line termination units 25 and 26 to each be an active system or a standby system. A switch core 271 passes frames to be transmitted to the line termination unit that operates as the active system.

Abstract: Wireless line termination units 21 and 22 respectively transmit and receive frames via wireless lines 51 and 52. Line termination units 25 and 26 respectively exchange frames with the wireless line termination units 21 and 22. The wireless lines 51 and 52 are treated as one virtual line. A radio monitoring unit 272 monitors the state of the wireless lines 51 and 52, and in accordance with the redundancy mode, instructs the wireless line termination units 21 and 22 to exchange copy frames with other wireless line termination unit and to abandon received frames. A communication path control unit 273 sets, in accordance with the monitoring result as to the state of the wireless lines by the radio monitoring unit 272, the line termination units 25 and 26 to each be an active system or a standby system. A switch core 271 passes frames to be transmitted to the line termination unit that operates as the active system.

Abstract: There is provided a network node device capable of selecting a route without causing an increase in the size and complexity of the information management system. Input lines (11-1 to 11-m) receive a data packet and transfer the received data packet to routing switching unit (12). Routing switching unit (12) extracts a character code address from the data packet received from input lines (11-1 to 11-m), uses this character code address as an identifier to search routing table (14), and determines an output line from output lines (13-1 to 13-n). Routing switching unit (12) transmits the received data packet through the determined output line.

Abstract: A packet scheduling apparatus which decreases a transmission delay and a transmission jitter of a premium packet which occur by transmitting a low priority packet and which efficiently transmits the low priority packet is provided. The apparatus includes a packet input section 1, a packet queue group 2, a scheduler section 3, a packet dividing section 4, a packet output section 5 and a packet buffer 6. The packet queue group 2 includes a premium packet queue 21 and a low priority packet queue 22. In addition, the scheduler section 3 includes a scheduling queue 31 and a scheduler 32. The “low priority packet” which influences the transmission of the “premium packet” is divided into a plurality of packets each having a length which falls within a transmission interval of the “premium packet” by the packet dividing section 4, and scheduled dynamically based on the transmission interval or load state of the “premium packet”.

Abstract: A fault management system for a switching equipment is disclosed by which, when an recoverable fault occurs with a processor or a circuit section of a switching equipment, a malfunction of an associated terminal equipment or the like or a fault of a physical layer in an associated apparatus can be detected without depending upon a manual operation of an operator. When a clock fault detection section detects that supply of a clock signal of a quartz oscillator which supplies the clock signal to a processor is interrupted, it notifies a concentrated fault management section of the result of the detection as an unrecoverable fault. The concentrated fault management section receives the notification and continuously signals reset signals for resetting the processor and a circuit section to the processor and the circuit section, respectively. Further, the concentrated fault management section sends a fault notification to a central control section connected to an external console.

Abstract: The present invention is provided with a pipeline for performing in a conveyor-belt style, the processing of obtaining the necessary information for performing an operation after judging the operation to be performed, of the Swap, the Push, and the Pop, and obtaining the output channel information, based on the content of the shim header of the MPLS packet and the information set in advance. The header controller sequentially supplies a top shim header of each packet received from a plurality of lines to the pipeline and performs an actual operation on the top shim header of each packet, based on the obtained information. As the result of the pop operation, when there exists a shim header that becomes a top newly, it repeats the above processing starting from a stage of supplying the shim header of the new top to the pipeline again. Namely, the pop processing of the MPLS packet is not collectively performed at once but performed by looping the pipeline.

Abstract: This invention is intended to eliminate an operation to copy the frame-relay frame, which was written in a memory through a frame transmission processing device, into another area excluding a memory table for the frame data, when a multiprotocol of a frame-relay frame is converted into a multiprotocol of the AAL5 frame. The frame-relay frame transmission circuit performs retrieval in the connection table and obtains the shift size by which the frame is to be shifted from the top address of a frame buffer. Then, the circuit searches the frame buffer, and transmits the frame buffer address with the shift information to a processor bus interface. The processor bus interface transmits the received frame to the address in the DMA transmission process.

Abstract: A packet scheduling apparatus which decreases a transmission delay and a transmission jitter of a premium packet which occur by transmitting a low priority packet and which efficiently transmits the low priority packet is provided. The apparatus includes a packet input section 1, a packet queue group 2, a scheduler section 3, a packet dividing section 4, a packet output section 5 and a packet buffer 6. The packet queue group 2 includes a premium packet queue 21 and a low priority packet queue 22. In addition, the scheduler section 3 includes a scheduling queue 31 and a scheduler 32. The “low priority packet” which influences the transmission of the “premium packet” is divided into a plurality of packets each having a length which falls within a transmission interval of the “premium packet” by the packet dividing section 4, and scheduled dynamically based on the transmission interval or load state of the “premium packet”.

Abstract: An asynchronous transfer mode (ATM) switching apparatus is provided in a communication network, and includes an ATM switch for switching a path for a cell. A control unit controls the ATM switch. A network interface board is installed in a slot to interface between the ATM switch and a communication channel for the cell. A server board is installed in a slot in which the network interface board can be installed. The server board receives cells from said communication channel through said network interface board and said ATM switch under control of the control unit to provide a service. The server board outputs cells corresponding to the service such that the cells are sent to the communication channel through the network interface board and the ATM switch under control of said control unit.

Abstract: The present invention is provided with a pipeline for performing in a conveyor-belt style, the processing of obtaining the necessary information for performing an operation after judging the operation to be performed, of the Swap, the Push, and the Pop, and obtaining the output channel information, based on the content of the shim header of the MPLS packet and the information set in advance. The header controller sequentially supplies a top shim header of each packet received from a plurality of lines to the pipeline and performs an actual operation on the top shim header of each packet, based on the obtained information. As the result of the pop operation, when there exists a shim header that becomes a top newly, it repeats the above processing starting from a stage of supplying the shim header of the new top to the pipeline again. Namely, the pop processing of the MPLS packet is not collectively performed at once but performed by looping the pipeline.

Abstract: An ATM cell forming device includes a memory, an SAR processing device, and a switch. The memory stores output channel information, cell header information, and frame information to be formed into cells. The SAR processing device assembles frame information into ATM cells by referring to the memory. The switch distributes the cells to the respective output channels. The SAR processing device includes an input frame distributing section, cell header read sections, and a cell assembly section. The input frame distributing section identifies output channels for pieces of frame information by referring to the memory on the basis of pieces of correspondence information, and distributes the pieces of frame information to the respective identified output channels.

Abstract: The invention provides a storage tank comprising a storage tank main body of concrete; lining plates lined on inner surfaces of a bottom, side walls, and a ceiling of the storage tank main body; and a manhole of the ceiling which is air- and liquid-tight and which blocks radiation. Leakage detection ditches are formed within welded seams of the lining plates. A method for manufacturing such a storage tank is also provided.