Abstract: A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.

Abstract: A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.

Abstract: A CD subcode transfer system includes a means for receiving a CD signal and outputting, along with a subcode, digital data derived from the CD signal after the digital data is error corrected and demodulated. The CD subcode transfer system also includes a means for determining whether a CRC check bit for Q channel data of the subcode is correct and for determining whether the Q channel data is correct upon comparison of the Q channel data with preceding Q channel data. In addition, the CD subcode transfer system includes a means for transferring the subcode and attaching the subcode to the digital data when the CRC check bit is determined to be correct and the Q channel data is determined to be correct.

Abstract: A multi-layered integrated semiconductor device incorporates an upper and lower IC chips which are connected with each other via a first set of wiring pads of the upper IC chip to a second set of wiring pads of the lower IC chip. The device is provided with a multiplicity of pair-wise connected external monitoring terminals on the periphery of the upper IC chip, and a multiplicity of monitoring pads on the lower IC chip, in opposition to the pair-wise connected monitoring pads, so that pad-to-pad resistances between the pads of the upper and lower IC chips can be externally measured by directly connecting the monitoring pads to the external terminals.

Abstract: A multi-layered integrated semiconductor device incorporates an upper and lower IC chips which are connected with each other via a first set of wiring pads of the upper IC chip to a second set of wiring pads of the lower IC chip. The device is provided with a multiplicity of pair-wise connected external monitoring terminals on the periphery of the upper IC chip, and a multiplicity of monitoring pads on the lower IC chip, in opposition to the pair-wise connected monitoring pads, so that pad-to-pad resistances between the pads of the upper and lower IC chips can be externally measured by directly connecting the monitoring pads to the external terminals.

Abstract: A one-chip microcomputer according to the present invention is provided with an initial reset circuit for producing a first initial reset signal having a first reset period and a second initial reset signal having a second reset period which is longer than the first reset period, an access circuit for gaining access to an address in a nonvolatile memory such as a built-in ROM to read data therefrom, and I/O buffer circuits. A storage circuit and an I/O buffer connected to a programmable I/O terminal are provided in the I/O buffer circuit and a function of the I/O terminal with options is selected in conformity with the data set in the storage circuit. The data stored at a predetermined address in the nonvolatile memory is transferred to the storage circuit by operating the access circuit until the termination of the reset period of the second initial reset signal after the termination of the first reset period of the first initial reset signal.

Abstract: A microcomputer in which an oscillating circuit provided therein is activated both when the microcomputer is in an activated state and when it is in a disabled state is provided with a changeover circuit for changing over a supply voltage of the oscillating circuit between when the microcomputer is in the activated state and in the disabled state. The changeover circuit supplies to the oscillating circuit a high voltage when the microcomputer is in the activated state and a low voltage when the microcomputer is in the disabled state. As a result, the starting characteristic when the power is turned on is not deteriorated. Further, the power consumption of the oscillating circuit when the microcomputer is in the disabled state is reduced.