Patents by Inventor Yoshifumi Kitayama

Yoshifumi Kitayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7071090
    Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: July 4, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazushi Higashi, Norihito Tsukahara, Takahiro Yonezawa, Yoshihiko Yagi, Yoshifumi Kitayama, Hiroyuki Otani
  • Publication number: 20050146029
    Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.
    Type: Application
    Filed: March 8, 2005
    Publication date: July 7, 2005
    Inventors: Kazushi Higashi, Norihito Tsukahara, Takahiro Yonezawa, Yoshihiko Yagi, Yoshifumi Kitayama, Hiroyuki Otani
  • Patent number: 6894387
    Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: May 17, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazushi Higashi, Norihito Tsukahara, Takahiro Yonezawa, Yoshihiko Yagi, Yoshifumi Kitayama, Hiroyuki Otani
  • Patent number: 6455099
    Abstract: A method and a device for applying a sealant to an IC having bumps, which can solve a cobwebbing problem when a dispense nozzle is raised after the sealant has been applied and implement a productivity improvement; specifically, a method and a device for applying a sealant to an IC having bumps, wherein a dispense nozzle (12) is raised in a first stage (E) at a low speed simultaneously with the stop of dispensing until the first stage (E) covers a specified height and then it is raised in a second stage (F) at a high seed. The above design, in which the dispense nozzle (12) is raised in the first stage (E) at a low speed after the application of the sealant (2) and the nozzle (12) is then raised at a high speed and in a short time in the second stage (F), can positively break off the sealant (2) without inducing cobwebbing and enhance productivity.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: September 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kouhei Enchi, Hiroyuki Yoshida, Yoshifumi Kitayama
  • Patent number: 6370750
    Abstract: The component (2) is first brought into point or line contact with the sheet (3) so as to avoid entrapment of air therebetween. The contact area between the component and the sheet is then gradually spread until the entire bottom surface of the component is adhered to the sheet.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: April 16, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuya Matsumura, Shoji Sato, Akihiro Yamamoto, Yoshifumi Kitayama, Yoichi Nakamura
  • Publication number: 20020022968
    Abstract: A recycling system is proposed which can retrieve reusable articles at a low cost. For example, a maker of welding wires ship the wires to a user with the wires wound on bobbins. The user sends a request for taking back empty bobbins to a center after consuming the welding wires. The center notifies a forwarder of a request for retrieval. The forwarder retrieves the empty bobbins from the user and bring them to a recycler. When the maker gives an order for empty bobbins to the center, the center notifies this to the recycler and the recycler ships the recycled bobbins to the maker.
    Type: Application
    Filed: June 20, 2001
    Publication date: February 21, 2002
    Inventors: Masaharu Shimada, Yoshifumi Kitayama
  • Patent number: 6332268
    Abstract: An IC chip (2) can be provided to a pre-mount process while being held on a tape-shaped supporting member (5), without being taken out of the tape-shaped supporting member (5).
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: December 25, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Imanishi, Yoshifumi Kitayama, Koichi Kumagai, Shinji Kanayama, Yoshinori Wada, Takahiro Yonezawa, Kazushi Higashi
  • Publication number: 20010005054
    Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.
    Type: Application
    Filed: January 25, 2001
    Publication date: June 28, 2001
    Inventors: Kazushi Higashi, Norihito Tsukahara, Takahiro Yonezawa, Yoshihiko Yagi, Yoshifumi Kitayama, Hiroyuki Otani
  • Patent number: 6207549
    Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: March 27, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazushi Higashi, Norihito Tsukahara, Takahiro Yonezawa, Yoshihiko Yagi, Yoshifumi Kitayama, Hiroyuki Otani
  • Patent number: 5791484
    Abstract: By a manufacturing method including a process of supplying a connection-releasable connecting material (4) onto a surface of a plurality of chip parts (3) and a process of connecting the plurality of chip parts (3) by the connecting material (4), there is formed a chip assembly (1) comprised of the plurality of chip parts (3) connected with each other by means of the releasable connecting material (4). Further provided is a method of preparing the chip assembly (1), a process of releasing connection achieved by the connecting material (4) between a target chip part and an adjacent chip part, and a process of mounting the target chip part separated through releasing of the connection onto a board and soldering the same, thereby providing chip parts capable of easily coping with an increase of operation speed of chip parts on the process of mounting line, achieving an improved space efficiency, and suppressing waste of resources.
    Type: Grant
    Filed: July 6, 1995
    Date of Patent: August 11, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Junji Ikeda, Osamu Yamazaki, Youichi Nakamura, Yoshifumi Kitayama
  • Patent number: 5744382
    Abstract: An electronic chip component includes an electrode formed on a wafer, a passivation film formed on the water, and an organic protective film covering an entire surface of exposed portions of the electrode and the passivation film. Such component is packed in a package including a carrier tape having therethrough a space for receiving the component with one end of such space open. A cover is applied to close the open end of the space after the component is inserted therein.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: April 28, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Kitayama, Kazuhiro Mori, Keiji Saeki, Takashi Akiguchi
  • Patent number: 5646439
    Abstract: An electronic chip component includes an electrode formed on a wafer, a passivation film formed on the wafer, and an organic protective film covering an entire surface of exposed portions of the electrode and the passivation film. A package for packing the component includes a carrier tape having therethrough a space for receiving the component with one end or side of the space opened, and a cover tape for closing the open end of the space after the component is stored in the space. A method for packing the component includes the steps of storing the component in the space of the carrier tape with one end of the space opened, and closing the open end of the space with the cover tape.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: July 8, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Kitayama, Kazuhiro Mori, Keiji Saeki, Takashi Akiguchi
  • Patent number: 5622590
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: April 22, 1997
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5550408
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in a matrix. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: August 27, 1996
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5436503
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: July 25, 1995
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5240170
    Abstract: A method for bonding leads of an IC component with electrodes of a circuit board includes the steps of using a mounting device to hold the IC component with flat portions of the leads inclined downward, mounting the IC component on the circuit board at a predetermined position thereof with the IC component held by the mounting device, moving the mounting device toward the circuit board to compress the IC component against the circuit board at the predetermined position while allowing the leads to flex to accommodate for nonuniformity in the heights of metal pieces to be bonded with the electrodes and bending of the circuit board. In this manner, the flat portions of the leads are brought into close contact with the electrodes. The leads are then irradiated with an optical beam so as to melt the metal pieces of the electrodes for bonding of the leads to the circuit board.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: August 31, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuto Nishida, Kazuhiro Nobori, Yoshifumi Kitayama, Keiji Saeki
  • Patent number: 5116228
    Abstract: A method and apparatus is provided for forming bumps on a plurality of IC chips arranged in a checkered pattern on a wafer. The bumps are formed from bump bases fixed to each IC chip. A forming tool having a recessed part of a height that is greater than the height of the bump bases is used to deform the bump bases into bumps. The forming tool is pressed by an elevating driving device against the bump bases under pressure sufficient to deform a respective part of each of the bump bases secured to each IC chip into a shape corresponding to that of the recess defined by the forming tool.
    Type: Grant
    Filed: October 23, 1989
    Date of Patent: May 26, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Kabeshita, Yoshifumi Kitayama
  • Patent number: 5012388
    Abstract: A chip type electronic component includes a main body having opposite first and second end surfaces and a lower surface defining a first plane. First and second electrode portions are respectively connected to the first and second end surfaces of the main body. Each of the first and second electrode portions includes a lower surface. Each lower surface of the first and second electrode portions includes a first planar face extending adjacent the main body in a second plane which is parallel to the first plane defined by the main body, and a second planar face extending adjacent the first planar face in a third plane which extends upwardly at an angle relative the second plane away from the main body. Accordingly, upon mounting of the chip type electronic component to a planar circuit board, a space is provided between the second planar face of each of the first and second electrode portions for accommodating solder materials.
    Type: Grant
    Filed: October 20, 1989
    Date of Patent: April 30, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Kabeshita, Tokuhito Hamane, Yoshifumi Kitayama
  • Patent number: 4676864
    Abstract: A bonding method of semiconductor device by using a film carrier; A heat-resistive insulating layer is deposited all over the surface of a dummy wafer on which a photo-resist film having a predetermined pattern is previously formed; The photo-resist film is removed together with the heat-resistive insulating layer for forming openings; Bumps are formed on the openings by plating using the heat-resistive insulating layer as a mask; After transferring the bumps to inner leads, the bumps of the inner leads are bonded to bonding pads of the semiconductor element.
    Type: Grant
    Filed: May 14, 1986
    Date of Patent: June 30, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Maeda, Yoshifumi Kitayama, Shuichi Murakami
  • Patent number: 4510011
    Abstract: A strip deforming apparatus for deforming a flexible strip into a looped endless band, comprising a first conveyor assembly comprising an endless belt having an upper travelling path, a second conveyor assembly positioned below the first conveyor assembly and comprising an endless belt having an upper travelling path parallel with and spaced apart downwardly from the belt of the first conveyor assembly, and a third conveyor assembly positoned between the first and second conveyor assemblies and comprising a pair of conveyor rolls elongated in longitudinal directions of the apparatus and each rotatable about the center axis thereof. At least one of the first and second conveyor assemblies is movable toward and away from the other conveyor assembly and the conveyor rolls are spaced apart in parallel from each other in a lateral direction of the apparatus.
    Type: Grant
    Filed: December 23, 1983
    Date of Patent: April 9, 1985
    Assignee: Bridgestone Tire Company Limited
    Inventors: Yusaku Azuma, Yoshifumi Kitayama, Shinji Kawaida