Abstract: On the basis of operation data, a wallpaper to be set on a wall object constructing a wall of a room is selected. Then, in a rendering process, a process of rendering the wall object and a first-type object arranged in the room by using a wallpaper texture corresponding to the set wallpaper, and a process of rendering a second-type object arranged in the room, are executed.

Abstract: When a predetermined instruction has been made on the basis of an operation input in a case where a positional relationship between a player character and an arrangement object satisfies a predetermined condition, the player character is caused to perform a predetermined action on the arrangement object. Then, on the basis of a virtual camera in a virtual space, a game image in which the player character and the arrangement object are included and in which a predetermined visual effect is added to the arrangement object on which the predetermined action has been performed is generated.

Abstract: An example of an information processing apparatus performs, in a predetermined area (e.g., a room) in a virtual space, editing including at least one of selecting a placement object to be placed in the area, placing the placement object, and moving the placement object, on the basis of an operation input. The information processing apparatus counts an editing time during which the editing is performed. The information processing apparatus stores, in a memory, arrangement data indicating arrangement of the placement object in the predetermined area. The information processing apparatus performs evaluation of the editing, based on at least the editing time such that a lower evaluation is given when the editing time is shorter than when the editing time is longer.

Abstract: A non-limiting information processing apparatus includes a processor, and the processor acquires a touch coordinate from an input device, and when a state is changed from a touch-off to a touch-on, plays an animation or video based on a touch position of the touch-on. Moreover, the processor changes, if detecting a slide when playing the animation or video, a speed of playing the animation or video based on a magnitude of the slide. The processor pauses playing of the animation or video if the touch-off is detected when playing the animation or video.

Abstract: A non-transitory storage medium encoded with a computer readable information processing program executed by an information processing apparatus is provided. The information processing apparatus includes a communication portion which exchanges data with an information storage medium through near field wireless communication. The information processing program causes the information processing apparatus to perform the following acts. The acts include writing available content information in the information storage medium, reading the available content information from the information storage medium, and updating availability of a content based on the read available content information.

Abstract: A non-limiting information processing apparatus includes a processor, and the processor acquires a touch coordinate from an input device, and when a state is changed from a touch-off to a touch-on, plays an animation or video based on a touch position of the touch-on. Moreover, the processor changes, if detecting a slide when playing the animation or video, a speed of playing the animation or video based on a magnitude of the slide. The processor pauses playing of the animation or video if the touch-off is detected when playing the animation or video.

Abstract: A non-transitory storage medium encoded with a computer readable information processing program executed by an information processing apparatus is provided. The information processing apparatus includes a communication portion which exchanges data with an information storage medium through near field wireless communication. The information processing program causes the information processing apparatus to perform the following acts. The acts include writing available content information in the information storage medium, reading the available content information from the information storage medium, and updating availability of a content based on the read available content information.

Abstract: Crowbar current in a CMOS amplifier circuit is limited during a transition state where one transistor is being turned on and another transistor is being turned off. The transistor that is being turned off is caused to pass through a midpoint state before the transistor that is being turned on is allowed to transition through a similar midpoint state. In one embodiment, independent gate voltages are applied to the P and N transistors of a CMOS amplifier. The gate voltages are independently controlled prior to passage through a midpoint level and then converge towards one another after passage through the midpoint state.

Abstract: In a CMOS FET IC element including at least one pair of transistors with connected drains, one an N-channel MOSFET and one a P-channel MOSFET, the N-channel MOSFET having a first threshold voltage controlled by the implantation of an ion, and the P-channel MOSFET having a second threshold voltage control are implanted with the same type of ion, so that one of the pair of transistors, either the N-channel MOSFET or the P-channel MOSFET is of a type that is normally ON, and the other MOSFET is of a type that is normally OFF with any gate voltage between the two voltages supplied to their sources.

Abstract: A circuit with an extremely small number of MOSFETs has a set of signals and their negatives as gate inputs to these MOSFETs which are serially connected into four rows. MOSFETs in different rows are interconected so as to produce the EXCLUSIVE-OR and the NOT-EXCLUSIVE-OR of these input signals.

Abstract: A semiconductor integrated circuit has a judgment circuit incorporated to determine whether or not an error correction function has operated. In particular, this enables detection of the operating condition of the error correction function in an integrated circuit with an error correction function incorporated, through the addition of a simple circuit, and in turn enables checking of whether the device was originally of good quality, or is one repaired by the addition of an error correction function to a defective device.

Abstract: A read control circuit for a read only memory implemented with MOSFETs includes a primary address line for selecting a desired memory cell group, and a secondary address line for selecting a desired data read line in the selected memory cell group. The thus selected data read line is charged to a desired level. Then, an address signal is applied to a desired row address line, whereby a discharging current representing the memory state flows through the selected memory cell and the data read line.

Abstract: A chip selection circuit connected to select one of a plurality of semiconductor circuits including at least one memory circuit for addressing purposes, comprises first and second circuit elements directly coupled to each other at a point, at least one of the first and second circuit elements comprising an MOS transistor where the gate electrode is connected to the source electrode, a power source being applied between the first and second circuit elements by the application of a first voltage to the first circuit element and a second voltage to the second circuit element, and an exclusive AND gate circuit provided for receiving the output from the point and chip selection enabling signals to provide chip selection signals.

Abstract: A ratioless semiconductor read only memory circuit comprises a plurality of insulated gate field-effect transistors being arranged in the form of a matrix consisting of columns and columns, bit lines of the rows of the transistors connected in parallel a sampling transistor connected in series to each of the rows of the transistors and each of the bit lines, and a row selection circuit connected to the respective bit lines for selecting one of the bit lines. The transistors of said array corresponding to individual bits are of the enhancement type or the depletion type depending on desired logic content.