Abstract: An apparatus that includes a plurality of first memory mats each including a plurality of common column sections except for at least one associated column section, the at least one associated column sections being selected by respective column addresses which are different from one another; and a second memory mat including the at least one corresponding column sections therein.

Abstract: Disclosed herein is an apparatus that includes a plurality of memory sections each including a plurality of word lines, a predecoder circuit configured to generate predecoded section address signals to select one of the plurality of memory sections and predecoded word line address signals to select one of the word lines included in a selected one of the plurality of memory sections based on a row address, and a section address control circuit configured to retain the predecoded section address signals regardless of an update of the row address in a test operation mode.

Abstract: Disclosed herein is an apparatus that includes a plurality of memory sections each including a plurality of word lines, a predecoder circuit configured to generate predecoded section address signals to select one of the plurality of memory sections and predecoded word line address signals to select one of the word lines included in a selected one of the plurality of memory sections based on a row address, and a section address control circuit configured to retain the predecoded section address signals regardless of an update of the row address in a test operation mode.

Abstract: Apparatuses and methods for signal line buffer timing control are disclosed. An example apparatus includes a plurality of signal lines including first and second control lines and further including data lines, and further includes first and second signal line buffers. The first signal line buffer includes first driver circuits configured to drive respective data signals on the data lines and to drive first and second control signals on the first and second control lines, respectively. The second signal line buffer includes second driver circuits configured to be activated to receive the data signals. The first and second control signals arrive at the second signal line buffer at different times. The second driver circuits are activated responsive a later one of active first and second control signals and are deactivated responsive to an earlier one of inactive first and second control signals.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.

Abstract: Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to turn the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.

Abstract: Apparatuses, systems, and methods for latch reset logic. Banks may have local latches which are coupled between a global data bus and the bank. Some of the local latches may be shared local latches which are coupled to a first bank and a second bank. The shared latches may latch data responsive to a first clock signal and a second clock signal, and may reset responsive to a combined reset signal. A reset logic circuit may receive the clock signals and a first and second reset signal. The reset logic circuit may provide the combined reset signal based on the first and second clock signals and reset signals. The clocks signals may be column active commands and the reset signals may be waveforms (e.g., falling edges) of row active commands used as part of access operations on the first or the second memory bank.

Abstract: Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to turn the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.

Abstract: Apparatuses and methods for signal line buffer timing control are disclosed. An example apparatus includes a plurality of signal lines including first and second control lines and further including data lines, and further includes first and second signal line buffers. The first signal line buffer includes first driver circuits configured to drive respective data signals on the data lines and to drive first and second control signals on the first and second control lines, respectively. The second signal line buffer includes second driver circuits configured to be activated to receive the data signals. The first and second control signals arrive at the second signal line buffer at different times. The second driver circuits are activated responsive a later one of active first and second control signals and are deactivated responsive to an earlier one of inactive first and second control signals.

Abstract: Apparatuses, systems, and methods for latch reset logic. Banks may have local latches which are coupled between a global data bus and the bank. Some of the local latches may be shared local latches which are coupled to a first bank and a second bank. The shared latches may latch data responsive to a first clock signal and a second clock signal, and may reset responsive to a combined reset signal. A reset logic circuit may receive the clock signals and a first and second reset signal. The reset logic circuit may provide the combined reset signal based on the first and second clock signals and reset signals. The clocks signals may be column active commands and the reset signals may be waveforms (e.g., falling edges) of row active commands used as part of access operations on the first or the second memory bank.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.

Abstract: Apparatuses and methods for signal line buffer timing control are disclosed. An example apparatus includes a plurality of signal lines including first and second control lines and further including data lines, and further includes first and second signal line buffers. The first signal line buffer includes first driver circuits configured to drive respective data signals on the data lines and to drive first and second control signals on the first and second control lines, respectively. The second signal line buffer includes second driver circuits configured to be activated to receive the data signals. The first and second control signals arrive at the second signal line buffer at different times. The second driver circuits are activated responsive a later one of active first and second control signals and are deactivated responsive to an earlier one of inactive first and second control signals.

Abstract: Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to bring the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.

Abstract: Apparatuses, systems, and methods for latch reset logic. Banks may have local latches which are coupled between a global data bus and the bank. Some of the local latches may be shared local latches which are coupled to a first bank and a second bank. The shared latches may latch data responsive to a first clock signal and a second clock signal, and may reset responsive to a combined reset signal. A reset logic circuit may receive the clock signals and a first and second reset signal. The reset logic circuit may provide the combined reset signal based on the first and second clock signals and reset signals. The clocks signals may be column active commands and the reset signals may be waveforms (e.g., falling edges) of row active commands used as part of access operations on the first or the second memory bank.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of detective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles: validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.