Patents by Inventor Yoshiharu Kanegae
Yoshiharu Kanegae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9503018Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: GrantFiled: November 17, 2015Date of Patent: November 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Publication number: 20160142011Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: ApplicationFiled: November 17, 2015Publication date: May 19, 2016Inventors: Toshiaki TSUTSUMI, Yoshihiro FUNATO, Tomonori OKUDAIRA, Tadato YAMAGATA, Akihisa UCHIDA, Takeshi TERASAKI, Tomohisa SUZUKI, Yoshiharu KANEGAE
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Patent number: 9252793Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: GrantFiled: November 29, 2010Date of Patent: February 2, 2016Assignee: Renesas Electronics CorporationInventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Patent number: 8816478Abstract: Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer.Type: GrantFiled: January 8, 2013Date of Patent: August 26, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Yoshiharu Kanegae, Hisashi Tanie, Mitsuhisa Watanabe, Keiyo Kusanagi
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Publication number: 20130314165Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.Type: ApplicationFiled: November 29, 2010Publication date: November 28, 2013Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
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Patent number: 8488277Abstract: A magnetic recording medium for a hard disk drive, including a thermal conduction layer made of materials having different thermal conductivities formed on a recording layer having data recording regions and including magnetic particles that are heated and cooled for magnetic recording, is provided based on a thermally assisted magnetic recording technique. First thin films made of a material high in thermal conductivity are formed on portions of the thermal conduction layer, said portions located in association with portions of the data recording regions. Second thin films made of a material lower in thermal conductivity than the first thin films are formed between respective pairs of the first thin films within the thermal conduction layer. The magnetic recording medium ensures the thermal stability of the magnetic particles heated for the magnetic recording, and the thermal stability of magnetic particles located near the heated magnetic particles, thereby suppressing disappearance of data.Type: GrantFiled: January 14, 2010Date of Patent: July 16, 2013Assignee: Hitachi, Ltd.Inventor: Yoshiharu Kanegae
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Publication number: 20120064374Abstract: Disclosed herein are a dot-patterned structure for magnetic recording bits and a magnetic recording medium provided therewith. The former exhibits high functionality and high performance owing to good crystallinity. The dot-patterned structure is composed of a first layer, which is continuous, and a second layer, which is discrete. The magnetic recording medium having a dot-patterned recording layer is formed by the steps of treating an underlying layer by lithography, thereby forming grooves, filling the grooves by epitaxial growth with the same material as the underlying layer, removing the photoresist used for lithography in a solvent, thereby forming pits, and filling the pits by epitaxial growth with a magnetic film as the recording layer.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Inventor: Yoshiharu Kanegae
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Publication number: 20100177426Abstract: A magnetic recording medium for a hard disk drive is provided based on a thermally assisted magnetic recording technique. The magnetic recording medium includes a recording layer and a thermal conduction layer. The thermal conduction layer is formed on the recording layer. The thermal conduction layer is made of materials having different thermal conductivities. The recording layer has data recording regions. First thin films made of a material highest in thermal conductivity among the materials are formed on some portions of the thermal conduction layer, with the some portions being located in association with portions of the data recording regions included in the recording layer. Second thin films made of a material relatively lower in thermal conductivity than the first thin films are formed between respective pairs of the first thin films within the thermal conduction layer. The recording layer includes magnetic particles that are heated and cooled for magnetic recording.Type: ApplicationFiled: January 14, 2010Publication date: July 15, 2010Inventor: Yoshiharu KANEGAE
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Publication number: 20090098413Abstract: Disclosed herein are a dot-patterned structure for magnetic recording bits and a magnetic recording medium provided therewith. The former exhibits high functionality and high performance owing to good crystallinity. The dot-patterned structure is composed of a first layer, which is continuous, and a second layer, which is discrete. The magnetic recording medium having a dot-patterned recording layer is formed by the steps of treating an underlying layer by lithography, thereby forming grooves, filling the grooves by epitaxial growth with the same material as the underlying layer, removing the photoresist used for lithography in a solvent, thereby forming pits, and filling the pits by epitaxial growth with a magnetic film as the recording layer.Type: ApplicationFiled: October 10, 2008Publication date: April 16, 2009Inventor: Yoshiharu KANEGAE
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Patent number: 7279739Abstract: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, the tunnel insulating film is formed by epitaxially growing a high-permittivity insulating film of HfO2, ZrO2 or CeO2 on a silicon or germanium substrate, or preferably, on a silicon or germanium (111) substrate. Also, the silicide nano-dots are formed on the tunnel insulating film.Type: GrantFiled: February 15, 2006Date of Patent: October 9, 2007Assignee: Hitachi, Ltd.Inventors: Yoshiharu Kanegae, Tomio Iwasaki
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Publication number: 20070126051Abstract: A semiconductor memory device having a stable characteristic and high reliability is achieved with formation of nano-dots with excellent interface stability. Source/drain diffusion layers are formed on a P-type silicon substrate to form a silicon oxide film. On this silicon oxide film, a silicon-rich oxide film is formed in a dot shape. On the silicon-rich oxide film, an interlayer dielectric made of SiO2 is formed. The silicon-rich oxide film has a property of storing charges in the film and excellent in stability of an interface with a silicon oxide film used for a tunneling dielectric. With this, a semiconductor memory device having a stable characteristic and high reliability is achieved with formation of nano-dots with excellent interface stability.Type: ApplicationFiled: December 6, 2006Publication date: June 7, 2007Applicant: Hitachi, Ltd.Inventor: Yoshiharu Kanegae
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Patent number: 7215566Abstract: A magnetic memory includes a TMR element in its memory layer, wherein the TMR element in the memory layer has ferromagnetic layers which are kept in tensile strain, the ferromagnetic layers having either Fe, Co or Ni, and a wiring layer adjacent to each of the ferromagnetic layers includes either Ru, W, Ir, Os or Mo, thereby increasing the magnetization.Type: GrantFiled: August 31, 2005Date of Patent: May 8, 2007Assignee: Hitachi, Ltd.Inventor: Yoshiharu Kanegae
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Patent number: 7180143Abstract: A semiconductor device constitutes an electric field effect type transistor having a semiconductor substrate, a gate insulating layer formed on the substrate and a gate electrode formed on the gate insulating layer. The gate insulating layer is mainly formed of silicon oxynitride (SiON) and a strain state of the gate insulating layer is a compressed strain state.Type: GrantFiled: August 4, 2004Date of Patent: February 20, 2007Assignee: Hitachi, Ltd.Inventors: Yoshiharu Kanegae, Tomio Iwasaki, Hiroshi Moriya
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Publication number: 20060180852Abstract: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, the tunnel insulating film is formed by epitaxially growing a high-permittivity insulating film of HfO2, ZrO2 or CeO2 on a silicon or germanium substrate, or preferably, on a silicon or germanium (111) substrate. Also, the silicide nano-dots are formed on the tunnel insulating film.Type: ApplicationFiled: February 15, 2006Publication date: August 17, 2006Inventors: Yoshiharu Kanegae, Tomio Iwasaki
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Publication number: 20060114714Abstract: A magnetic memory includes a TMR element in its memory layer, wherein the TMR element in the memory layer has ferromagnetic layers which are kept in tensile strain, the ferromagnetic layers having either Fe, Co or Ni, and a wiring layer adjacent to each of the ferromagnetic layers includes either Ru, W, Ir, Os or Mo, thereby increasing the magnetization.Type: ApplicationFiled: August 31, 2005Publication date: June 1, 2006Inventor: Yoshiharu Kanegae
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Publication number: 20050051855Abstract: A semiconductor device constitutes an electric field effect type transistor having a semiconductor substrate, a gate insulating layer formed on the substrate and a gate electrode formed on the gate insulating layer. The gate insulating layer is mainly formed of silicon oxynitride (SiON) and a strain state of the gate insulating layer is a compressed strain state.Type: ApplicationFiled: August 4, 2004Publication date: March 10, 2005Inventors: Yoshiharu Kanegae, Tomio Iwasaki, Hiroshi Moriya