Abstract: A semiconductor device, a testing method and a refresh control method having a temperature detecting function to detect a predetermined temperature with little dispersion and to optimize the acting state in accordance with the predetermined temperature detected. The semiconductor device includes at least a memory cell, a refresh control circuit for switching the refresh period tREF of the memory cell, and a temperature detecting unit to be biased with a bias voltage VB+ coming from a voltage bias unit including a reference unit and a regulator unit.

Abstract: A semiconductor memory device having a driver transistor for the supply of electric power is provided, which can diminish leakage current during inactivation while ensuring sufficient power supply capability for a sense amplifier during activation. Gate width is provided at every two bit line pair pitches perpendicularly to a bit line direction, and a supply voltage VDD and a reference voltage VSS are fed to PMOS transistors SP0, SP0_ to SP3, sP3_ and NMOS transistors SN0, SN0_ to SN3, SN3_. In driver-dedicated PMOS transistors P1, P2, and NMOS transistors N1, N2, gate width is adjusted using the length of two bit line pair pitches as a maximum value, while gate length is adjusted using an adjusting region &Dgr;L, whereby there can be obtained driver-dedicated MOS transistors P1, P2, N1, and N2 in an appropriately adjusted state with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and diminishing a tailing current.

Abstract: A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

Abstract: A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal &phgr;CPR. The signal &phgr;CPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

Abstract: It is intended to provide a control method of a semiconductor memory device and a semiconductor memory device capable of shortening pre-charge operation time that comes after termination of successive data access operation, namely, successive data read/write operation, without causing deterioration of restore voltage to memory cells and delay of initial data access time. An activated word line WL0 is deactivated with appropriate timing that is between time after bit line pairs (BL0 and /BL0, . . . BLN and /BLN) are differentially amplified up to full amplitude voltage level and time where column selecting lines CL0, . . . CLN are selected. That is, deactivation time &tgr;A for the word line can be embedded in a period of successive data access operation. Pre-charge operation can be terminated within time that is a sum of deactivation time &tgr;AB of a sense amplifier and equalizing time &tgr;C of the bit line pairs. Thereby, pre-charge period can be shortened.

Abstract: There is provided an inventive semiconductor memory device and control method thereof capable of preventing shift operation to deactivated state and data access due to transition of address signals from occurring concurrently without accompanying delay of access time, thereby to prevent data-holding characteristic of memory cell from deteriorating. A column selecting circuit 16 is deactivated based on an input signal EXBn outputted to a glitch canceller 20 prior to precharge signal PRE so as to prevent selection of a column selecting signal CLn and deactivation of a word line WL from occurring concurrently. This manner substitutes for taking delay time &tgr;D that is to be added to signals CAGn from which glitch noises due to transition of address CAn are eliminated.

Abstract: The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).

Abstract: The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

Abstract: In the case that a refresh operation is carried out which is independent from an external access operation, both a data access method of a semiconductor memory device, and a semiconductor memory device are provided by which time suitable of each of these external access operation and refresh operation is set. While a time-measuring start signal “SIN” is entered into a path switching means, the path switching means is connected to either a first timer section or a second timer section under control of an external-access-operation-start-request signal REQ(O) and a refresh-operation-start-request signal REQ(I). Both the first and second timer sections measure both time “&tgr;O” and time “&tgr;I” to output a time-measuring stop signal “SOUT.

Abstract: There is provided a semiconductor memory device and a redundancy judging method which can reduce current consumption when a static-type redundancy judging operation is performed. In case absence of substitute to auxiliary memory cells is set, a non-redundancy setting signal Jdg is set in high logic level and the comparing unit 3 is inactivated and has an operation thereof stopped. Logic fixing unit 5 is connected to respective comparison results E0-n. The logic fixing unit 5 is activated in response to the non-redundancy setting signal Jdg of high logic level and fixes the respective comparison results E0-n to a predetermined logic level. The predetermined logic level is a value which indicates the discordance of the comparison results E0-n and hence, logic composing unit 7 judges that address information and redundancy address information discord with each other.

Abstract: A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal &phgr;CPR. The signal &phgr;CPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

Abstract: A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

Abstract: A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

Abstract: A semiconductor device, a testing method and a refresh control method having a temperature detecting function to detect a predetermined temperature with little dispersion and to optimize the acting state in accordance with the predetermined temperature detected. The semiconductor device comprises: a memory cell 26; a refresh control circuit 25 for switching the refresh period tREF of the memory cell; and a temperature detecting unit 12A to be biased with a bias voltage VB+ coming from a voltage bias unit 11 including a reference unit 13 and a regulator unit 14.

Abstract: A duplex memory control apparatus having a first control unit containing a first memory and a second control unit containing second memory, a first control unit and a second control unit connected to each other through a bus.

Abstract: A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.

Abstract: An IC chip is provided with a wireless unit for inputting and outputting data by wireless communication, in addition to a logic section, so that the IC chip no longer needs I/O pads, leaving only power supply and ground pads. IC chips can input and output data with one another by wireless communications, which makes it possible to significantly improve the spacing relationships of various chips on a singular or even plurality of substrates.

Abstract: The sending/receiving unit of an STM switch is provided with a converting circuit for converting time division multiplexed frames of an STM network to cells of an ATM network and a converting circuit for converting cells of an ATM network to time division multiplexed frames of an STM network. The STM switch time division multiplexes data from terminals, converts the time division multiplexed frame to cells and sends the cells to an ATM switch. Cells switched by an ATM switch and sent to the STM switch are converted to time division multiplexed frames by the STM switch, whence the frames are sent to prescribed terminals.

Abstract: A semiconductor memory device including a memory cell for holding charge of first cell information or second cell information, a word line connected to the memory cell for supplying the memory cell with word line voltage, a bit line connected to the memory cell for conveying charge corresponding to the first or second cell information, a dummy cell connected to the bit line for supplying the bit line with complementary charge, and a dummy word line connected to the dummy cell for supplying the dummy cell with dummy word line voltage. The first cell information is read based on the charge conveyed to the bit line from the memory cell when the word line is activated, and the second cell information is read based on the complementary charge supplied to the bit line from the dummy cell when the dummy word line is activated.

Abstract: An exchange equipment using STM able to achieve an improvement of an efficiency of use and an improvement of ease of increase of terminal cards, that is, an STM type exchange, including a time switch, for performing exchange processing of time division multiplexed data, wherein a ring highway is connected via a terminal common unit to an upstream highway and a downstream highway coupled to this time switch via a highway interface unit or directly and wherein a plurality of terminal cards are connected to this ring highway. Each terminal card is provided with an add/drop unit which drops and adds the data from and to an assigned time slot on the ring highway according to control information indicating time slot assignment information determined by the control unit and adds the data and with a card control unit which controls the add/drop unit.