Abstract: Provided are a denitration catalyst regeneration method and a denitration catalyst regeneration system, which are capable of recovering denitration performance to a high level and reducing the SO2 oxidation rate of a catalyst. A denitration catalyst regeneration method according to the present invention includes: a chemical solution cleaning step for immersing a denitration catalyst in a chemical solution containing a fluorine compound and an inorganic acid; a step for extracting the denitration catalyst from the chemical solution; and a finish washing step for washing the denitration catalyst extracted from the chemical solution with a finish cleaning solution containing an organic acid.

Abstract: A communication system includes: a first communication device configured to include first buffers to store data to be transmitted and received; a second communication device configured to include second buffers to store data to be transmitted and received; and a failure control device configured to include: an obtainment unit configured to obtain buffer usage state information to indicate a state of use of each of the first buffers and the second buffers from each of the first communication device and the second communication device; and an identification unit configured to identify a failure occurrence site on a channel, based on the obtained buffer usage state information, wherein the first communication device is configured to transmit and receive the data via the channel to and from the second communication device.

Abstract: A storage control device includes a first processor, a second processor, and transfer units for transferring data from the first processor to the second processor. The first processor receives a write request for writing first data from a first device and sequentially transmits the first data, additional data, and pieces of dummy data. A number of the pieces is same as a number of the transfer units. The first processor notifies the first device of completion of the writing upon receiving an acknowledgement for a last transmitted piece of dummy data. Each transfer unit includes a third processor. The third processor receives the additional data from a preceding processor, and transmits an acknowledgement to the preceding processor upon storing the received additional data. The third processor receives one piece of dummy data from the preceding processor, and transmits an acknowledgement to the preceding processor upon storing the one piece.

Abstract: A storage control device includes a first processor, a second processor, and transfer units for transferring data from the first processor to the second processor. The first processor receives a write request for writing first data from a first device and sequentially transmits the first data, additional data, and pieces of dummy data. A number of the pieces is same as a number of the transfer units. The first processor notifies the first device of completion of the writing upon receiving an acknowledgement for a last transmitted piece of dummy data. Each transfer unit includes a third processor. The third processor receives the additional data from a preceding processor, and transmits an acknowledgement to the preceding processor upon storing the received additional data. The third processor receives one piece of dummy data from the preceding processor, and transmits an acknowledgement to the preceding processor upon storing the one piece.

Abstract: A communication system includes: a first communication device configured to include first buffers to store data to be transmitted and received; a second communication device configured to include second buffers to store data to be transmitted and received; and a failure control device configured to include: an obtainment unit configured to obtain buffer usage state information to indicate a state of use of each of the first buffers and the second buffers from each of the first communication device and the second communication device; and an identification unit configured to identify a failure occurrence site on a channel, based on the obtained buffer usage state information, wherein the first communication device is configured to transmit and receive the data via the channel to and from the second communication device.

Abstract: Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.

Abstract: A semiconductor device includes multiple transistors (70, 75, 80, 85), each of the transistors (70, 75, 80, 85) including a gate electrode (18) formed above a semiconductor substrate (30), source/drain regions (10, 12, 14, 16) formed on both sides of the gate electrode (18), and a charge storage layer (38) interposed between the gate electrode (18) and the semiconductor substrate (30). One of the source/drain regions (10, 12, 14, 16) of adjacent transistors (70, 75, 80, 85) is respectively connected in series, so the above-mentioned multiple transistors (70, 75, 80, 85) form a closed loop in the semiconductor device. Accordingly, it is possible to provide a semiconductor device (60) in which the circuit function of the logic circuit (64) can be reconfigured in a non-volatile manner, thereby enabling wide selectivity and excellent design facility in terms of the circuit design and making it possible to readily fabricate the logic circuit (64) and a non-volatile memory (62) on a single chip (60).

Abstract: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.

Abstract: Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.

Abstract: Provided is a memory control apparatus including: a monitoring unit that monitors, for each of the masters, a usable bandwidth indicating an amount of memory access data to be accessed per unit time in response to a corresponding one of the access requests from the master; a holding unit that holds a predetermined request bandwidth for each of the masters; a bandwidth determining unit that determines whether or not the usable bandwidth has reached the predetermined request bandwidth for each of the masters; and a control unit that issues an advanced refresh command to the memory based on a result of the determination by the bandwidth determining unit for each of the masters, regardless of timing of a refresh cycle.

Abstract: An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.

Abstract: An ultra high strength fiber-reinforced cement composition includes cement, silica fume, coal gasification fly ash, insoluble anhydrous gypsum, and metal fiber having a length between 5 and 30 mm and a diameter of between 0.1 and 1 mm. The coal gasification fly ash is spherical fine particles having a maximum particle size between 5 and 10 ?m. Mass ratio of the silica fume: the coal gasification fly ash is 95 through 50 portions: 5 through 50 portions.

Abstract: A cement admixture for concrete using a polycarboxylate based water reducing agent that can produce light concrete with little slump loss and good workability that prevents dragging and the like and having no material separation, and a cement composition using the cement admixture are provided. A cement admixture for concrete using a polycarboxylate based water reducing agent, comprising bentonites (one or more selected from a group comprising bentonite, acidic white clay and active white clay are preferable) and polyvinyl alcohol, or the cement admixture further compounding saccharides. A cement composition, wherein cement, a polycarboxylate based water reducing agent, bentonites and polyvinyl alcohol are main components, or the cement composition, further compounding saccharides. Preferably, the cement composition, wherein the polycarboxylate based water reducing agent is 0.3 to 5 parts based on 100 parts of cement, bentonites are 0.1 to 10 parts, polyvinyl alcohol is 0.03 to 1 part and saccharides are 0.

Abstract: The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: A memory access controller includes: an access request bank analyzer which generates access request bank information indicative of a bank of a memory to be accessed according to a memory access request signal; a bank use state information holder for holding the access request bank information for a predetermined period to use the held information as bank use state information; and an access permission signal generator for generating, based on the access request bank information and the bank use state information, an access permission signal which is to be used for controlling whether or not to accept a subsequent memory bank access. The bank use state information regarding an access-permitted memory bank is updated according to the access information, such as transfer direction information, access unit information, memory initialization information, etc.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.

Abstract: A semiconductor device includes multiple transistors (70, 75, 80, 85), each of the transistors (70, 75, 80, 85) including a gate electrode (18) formed above a semiconductor substrate (30), source/drain regions (10, 12, 14, 16) formed on both sides of the gate electrode (18), and a charge storage layer (38) interposed between the gate electrode (18) and the semiconductor substrate (30). One of the source/drain regions (10, 12, 14, 16) of adjacent transistors (70, 75, 80, 85) is respectively connected in series, so the above-mentioned multiple transistors (70, 75, 80, 85) form a closed loop in the semiconductor device. Accordingly, it is possible to provide a semiconductor device (60) in which the circuit function of the logic circuit (64) can be reconfigured in a non-volatile manner, thereby enabling wide selectivity and excellent design facility in terms of the circuit design and making it possible to readily fabricate the logic circuit (64) and a non-volatile memory (62) on a single chip (60).