Patents by Inventor Yoshiharu Yoshizawa
Yoshiharu Yoshizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11070352Abstract: A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.Type: GrantFiled: August 27, 2020Date of Patent: July 20, 2021Assignee: FUJITSU LIMITEDInventors: Nobuaki Kawasoe, Yoshiharu Yoshizawa, Manabu Yamazaki
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Publication number: 20210067312Abstract: A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.Type: ApplicationFiled: August 27, 2020Publication date: March 4, 2021Applicant: FUJITSU LIMITEDInventors: Nobuaki Kawasoe, Yoshiharu YOSHIZAWA, MANABU YAMAZAKI
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Patent number: 10284302Abstract: An optical transmitter includes an optical modulator that includes a first phase shifter for a most significant bit, a second phase shifter for a least significant bit, and a third phase shifter for fine adjustment, the first phase shifter, the second phase shifter, and the third phase shifter are disposed along an optical waveguide, and a drive circuit that includes a first driver that drives the first phase shifter, a second driver that drives the second phase shifter, and a third driver that drives the third phase shifter, wherein a drive polarity of the third driver is adjustable in a positive direction and a negative direction, and the third phase shifter adjusts an amount of phase change of the optical modulator in a positive direction or a negative direction based on a drive voltage inputted from the third driver.Type: GrantFiled: May 23, 2018Date of Patent: May 7, 2019Assignee: FUJITSU LIMITEDInventors: Shigeki Kawaai, Yoshiharu Yoshizawa, Manabu Yamazaki, Daisuke Usui
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Publication number: 20180343064Abstract: An optical transmitter includes an optical modulator that includes a first phase shifter for a most significant bit, a second phase shifter for a least significant bit, and a third phase shifter for fine adjustment, the first phase shifter, the second phase shifter, and the third phase shifter are disposed along an optical waveguide, and a drive circuit that includes a first driver that drives the first phase shifter, a second driver that drives the second phase shifter, and a third driver that drives the third phase shifter, wherein a drive polarity of the third driver is adjustable in a positive direction and a negative direction, and the third phase shifter adjusts an amount of phase change of the optical modulator in a positive direction or a negative direction based on a drive voltage inputted from the third driver.Type: ApplicationFiled: May 23, 2018Publication date: November 29, 2018Applicant: FUJITSU LIMITEDInventors: Shigeki Kawaai, Yoshiharu Yoshizawa, Manabu Yamazaki, Daisuke Usui
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Patent number: 9742413Abstract: An electronic device includes: a voltage controlled delay line including delay elements configured to delay an input clock signal and output the clock signal, a delay control element configured to control a delay time of the clock signal delayed by the delay elements in accordance with a control voltage, a delay sensitivity adjustment circuit configured to adjust a ratio of an amount of change of the delay time to an amount of change of the control voltage, and a plurality of delay circuits; and a control voltage generation circuit configured to compare a phase of an output signal of any one of the plurality of delay circuits and a phase of the clock signal, generate the control voltage so as to match the phase of the output signal and the phase of the clock signal based on the comparison result, and output the control voltage to the delay control element.Type: GrantFiled: June 18, 2015Date of Patent: August 22, 2017Assignee: FUJITSU LIMITEDInventors: Yoshiharu Yoshizawa, Masazumi Maeda
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Patent number: 9571110Abstract: A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers.Type: GrantFiled: August 26, 2015Date of Patent: February 14, 2017Assignee: FUJITSU LIMITEDInventors: Masazumi Maeda, Yoshiharu Yoshizawa
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Patent number: 9362877Abstract: An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.Type: GrantFiled: May 12, 2014Date of Patent: June 7, 2016Assignee: FUJITSU LIMITEDInventors: Masazumi Maeda, Yoshiharu Yoshizawa
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Publication number: 20160105189Abstract: A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers.Type: ApplicationFiled: August 26, 2015Publication date: April 14, 2016Inventors: Masazumi MAEDA, Yoshiharu YOSHIZAWA
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Publication number: 20160028409Abstract: An electronic device includes: a voltage controlled delay line including delay elements configured to delay an input clock signal and output the clock signal, a delay control element configured to control a delay time of the clock signal delayed by the delay elements in accordance with a control voltage, a delay sensitivity adjustment circuit configured to adjust a ratio of an amount of change of the delay time to an amount of change of the control voltage, and a plurality of delay circuits; and a control voltage generation circuit configured to compare a phase of an output signal of any one of the plurality of delay circuits and a phase of the clock signal, generate the control voltage so as to match the phase of the output signal and the phase of the clock signal based on the comparison result, and output the control voltage to the delay control element.Type: ApplicationFiled: June 18, 2015Publication date: January 28, 2016Inventors: Yoshiharu YOSHIZAWA, Masazumi MAEDA
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Publication number: 20150002205Abstract: An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.Type: ApplicationFiled: May 12, 2014Publication date: January 1, 2015Applicant: FUJITSU LIMITEDInventors: Masazumi Maeda, Yoshiharu Yoshizawa
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Patent number: 8149033Abstract: A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.Type: GrantFiled: October 6, 2010Date of Patent: April 3, 2012Assignee: Fujitsu LimitedInventors: Yoshiharu Yoshizawa, Yoshito Koyama
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Patent number: 8089308Abstract: In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.Type: GrantFiled: April 10, 2009Date of Patent: January 3, 2012Assignee: Fujitsu LimitedInventors: Yoshiharu Yoshizawa, Yoshito Koyama
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Patent number: 8049542Abstract: In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.Type: GrantFiled: April 10, 2009Date of Patent: November 1, 2011Assignee: Fujitsu LimitedInventors: Yoshiharu Yoshizawa, Yoshito Koyama
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Publication number: 20110018601Abstract: A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.Type: ApplicationFiled: October 6, 2010Publication date: January 27, 2011Applicant: FUJITSU LIMITEDInventors: Yoshiharu Yoshizawa, Yoshito Koyama
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Publication number: 20090256605Abstract: In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.Type: ApplicationFiled: April 10, 2009Publication date: October 15, 2009Applicant: FUJITSU LIMITEDInventors: Yoshiharu YOSHIZAWA, Yoshito KOYAMA