Abstract: A method is disclosed for the manufacture of a multilayered interconnect structure on an insulating substrate. First and second conductive layers are formed on one and on the other (reverse) surfaces, respectively, of the insulating substrate. An insulating layer is formed, by means of a plasma CVD method, on the surface of the insulating substrate, to electrical insulation between interconnect layers. This is followed by a reactive ion etching step. This results in the formation of the aforementioned layer of a uniform thickness and having a uniform etching rate. That is, with the conductive layer formed on the rear surface of the insulating substrate, the complete insulating substrate is placed at the same potential level, whereby a uniform electrochemical reaction occurs on the surface thereof, resulting in the formation of the layers having a uniform etching rate, and in the formation of these layers each having the same thickness.

Abstract: The invention provides a method for manufacturing a semiconductor device, having the steps of: forming a first mask member which has an opening to expose a desired portion of one major surface of a semiconductor substrate; doping an impurity which has the same conductivity type as that of the semiconductor substrate through the opening of the first mask member to form an impurity region of a high concentration in the surface layer of the semiconductor substrate; forming a second mask member on the side surface of the opening of the first mask member while the first mask member is left as it is; forming a groove by selectively etching the semiconductor substrate using the first and second mask members, and at the same time leaving an impurity region of the high concentration at least on the side surface of the groove; and burying an insulating isolation material in the groove.

Abstract: The invention provides a method for manufacturing a semiconductor device, having the steps of: forming a first mask pattern on a semiconductor layer through an SiO.sub.2 film; forming a thin layer on at least side surfaces of the first mask pattern; selectively forming a second mask pattern on an SiO.sub.2 film portion located between the thin layer portions formed on the side surface of the first mask pattern; selectively etching the thin layer portions formed on the at least side surfaces of the first mask pattern, and the SiO.sub.2 film portions under the thin layer portions formed on the side surfaces of the first mask pattern, using the first and second mask patterns; selectively etching an exposed portion of the semiconductor layer to form a trench; and forming an element isolation region by burying an insulating material in the trench.

Abstract: In gas phase growth of a polysilicon layer on a semiconductor substrate, a silicon layer of a single-crystal structure or a structure akin thereto may be formed only on an exposed surface of the substrate surrounded by an insulating film for element isolation by applying an energy beam to the substrate. A semiconductor device obtained by forming such an element as an MOS transistor on the silicon layer is free from any difference in level between an element region and an element isolation region, and hence from snapping or disconnection of any wiring traversing the boundary between those regions.

Abstract: A first level interconnection layer of substantially a given width is formed on an insulating film on a semiconductor substrate. At least two second level interconnection layers, which cross the first level interconnection layer on another insulating layer, are formed. In a step for forming the first level interconnection layer, projections are formed at each side of the first level interconnection layer between the crossings of the second level interconnection layers. The total width of the first level interconnection layer including the width of the projection is larger than the given width. After the second level interconnection layers are formed, the projections of the first level interconnection layer are removed along with any second level interconnection layer material remaining intermediate the second level interconnection layers, thereby to prevent short-circuiting between the second level interconnection layers.