Abstract: An object of the present invention is to increase a writing speed to a flash memory while suppressing an increase in noise. In the high-speed write mode, the memory controller simultaneously performs a first write operation with a second write current having a current value smaller than the first write current with respect to a second number of memory cells having a larger number than the first write current. At the completion of the first write operation, the memory controller simultaneously performs the second write operation by the third write current having a larger current value than the second write current with respect to the memory cell determined by the sense amplifier to have not completed the write operation in the determination process.

Abstract: To provide an information processing apparatus, a reading control method, and a computer readable storage medium that can improve the secrecy of information written in a secret area compared with the case of controlling access only by authentication, the information processing apparatus includes a nonvolatile memory that has a secret area where secret information is stored, an authentication controller that authenticates access to the nonvolatile memory, a flag information storage unit that stores flag information, and a memory controller that controls access to the nonvolatile memory by using the flag information stored in the flag information storage unit. The memory controller allows reading of the secret information from the secret area when a value of the flag information is a specified value and validity of access is authenticated by the authentication controller.

Abstract: An object of the present invention is to increase a writing speed to a flash memory while suppressing an increase in noise. In the high-speed write mode, the memory controller simultaneously performs a first write operation with a second write current having a current value smaller than the first write current with respect to a second number of memory cells having a larger number than the first write current. At the completion of the first write operation, the memory controller simultaneously performs the second write operation by the third write current having a larger current value than the second write current with respect to the memory cell determined by the sense amplifier to have not completed the write operation in the determination process.

Abstract: To provide an information processing apparatus, a reading control method, and a computer readable storage medium that can improve the secrecy of information written in a secret area compared with the case of controlling access only by authentication, the information processing apparatus includes a nonvolatile memory (2) that has a secret area (6) where secret information is stored, an authentication controller (4) that authenticates access to the nonvolatile memory (2), a flag information storage unit (3) that stores flag information, and a memory controller (5) that controls access to the nonvolatile memory (2) by using the flag information stored in the flag information storage unit (3). The memory controller (5) allows reading of the secret information from the secret area (6) when a value of the flag information is a specified value and validity of access is authenticated by the authentication controller (4).

Abstract: An object of the present invention is to provide a sealing device and a sealing method with which oxygen substitution can be sufficiently carried out even in a bag-like container. The present invention is a sealing device for putting a content into a bag-like container and sealing the container, and includes a content supply portion that supplies the content to the container having an opening in an open state, an inert gas supply portion that supplies inert gas to the container, a liquefied inert gas supply portion that supplies liquefied inert gas to the container, and a sealing portion that seals the opening of the container after the liquefied inert gas is supplied.

Abstract: A sensitivity analysis system has a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor device is stored. The interconnect structure has: a main interconnection; and a contact structure electrically connected to the main interconnection and extending toward a semiconductor substrate. Parameters contribute to parasitic capacitance of the interconnect structure, and variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range.

Abstract: A semiconductor device has an interconnect structure that includes a main interconnection and a contact structure. Parameters contributing to parasitic capacitance and interconnect resistance of the interconnect structure include: main parameters including width/thickness of the main interconnection; and sub parameter. Variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. A method of designing the semiconductor device includes: calculating the maximum capacitance value, the minimum capacitance value, the maximum resistance value and the minimum resistance value of the interconnect structure under a condition that respective variation amplitudes of the main parameters do not simultaneously take maximum values and variation of the sub parameter is fixed to a predetermined value; generating a CR-added netlist; and performing operation verification of the semiconductor device by using the CR-added netlist.

Abstract: A semiconductor device has an interconnect structure that includes a main interconnection and a contact structure. Parameters contributing to parasitic capacitance and interconnect resistance of the interconnect structure include: main parameters including width/thickness of the main interconnection; and sub parameter. Variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. A method of designing the semiconductor device includes: calculating the maximum capacitance value, the minimum capacitance value, the maximum resistance value and the minimum resistance value of the interconnect structure under a condition that respective variation amplitudes of the main parameters do not simultaneously take maximum values and variation of the sub parameter is fixed to a predetermined value; generating a CR-added netlist; and performing operation verification of the semiconductor device by using the CR-added netlist.

Abstract: A sensitivity analysis system has a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor device is stored. The interconnect structure has: a main interconnection; and a contact structure electrically connected to the main interconnection and extending toward a semiconductor substrate. Parameters contribute to parasitic capacitance of the interconnect structure, and variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range.

Abstract: A process management method for managing manufacturing variability of an interconnection included in a semiconductor device is provided. The process management method includes: calculating interconnect resistance and interconnect capacitance regarding an interconnection included in the semiconductor device, under a condition that manufacturing variability of a width and a thickness of the interconnection is expressed by points on a predetermined circle of equal probability of a joint probability density function; and defining, based on the calculated interconnect resistance and interconnect capacitance, a variation range of interconnect resistance and interconnect capacitance caused by manufacturing variability. The variation range is defined two-dimensionally in a coordinate system where a first axis represents interconnect resistance and a second axis represents interconnect capacitance.